| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <202006041810.6bEH9qnx%lkp@intel.com>
Date: Thu, 4 Jun 2020 19:02:03 +0800
From: kernel test robot <lkp@...el.com>
To: "Ooi, Joyce" <joyce.ooi@...el.com>,
Thor Thayer <thor.thayer@...ux.intel.com>,
"David S . Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>
Cc: kbuild-all@...ts.01.org, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org,
Dalon Westergreen <dalon.westergreen@...ux.intel.com>,
Joyce Ooi <joyce.ooi@...el.com>,
Tan Ley Foon <ley.foon.tan@...el.com>,
See Chin Liang <chin.liang.see@...el.com>,
Dinh Nguyen <dinh.nguyen@...el.com>
Subject: Re: [PATCH v3 09/10] net: eth: altera: add msgdma prefetcher
Hi Joyce",
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on net/master]
[also build test WARNING on robh/for-next sparc-next/master linus/master v5.7 next-20200604]
[cannot apply to net-next/master]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Ooi-Joyce/net-eth-altera-tse-Add-PTP-and-mSGDMA-prefetcher/20200604-153632
base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git bdc48fa11e46f867ea4d75fa59ee87a7f48be144
config: arc-allyesconfig (attached as .config)
compiler: arc-elf-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
drivers/net/ethernet/altera/altera_msgdma_prefetcher.c: In function 'msgdma_pref_initialize':
>> drivers/net/ethernet/altera/altera_msgdma_prefetcher.c:97:49: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'dma_addr_t' {aka 'long long unsigned int'} [-Wformat=]
97 | netdev_info(priv->dev, "%s: RX Desc mem at 0x%xn", __func__,
| ~^
| |
| unsigned int
| %llx
98 | priv->pref_rxdescphys);
| ~~~~~~~~~~~~~~~~~~~~~
| |
| dma_addr_t {aka long long unsigned int}
drivers/net/ethernet/altera/altera_msgdma_prefetcher.c:101:49: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'dma_addr_t' {aka 'long long unsigned int'} [-Wformat=]
101 | netdev_info(priv->dev, "%s: TX Desc mem at 0x%xn", __func__,
| ~^
| |
| unsigned int
| %llx
102 | priv->pref_txdescphys);
| ~~~~~~~~~~~~~~~~~~~~~
| |
| dma_addr_t {aka long long unsigned int}
vim +97 drivers/net/ethernet/altera/altera_msgdma_prefetcher.c
18
19 int msgdma_pref_initialize(struct altera_tse_private *priv)
20 {
21 int i;
22 struct msgdma_pref_extended_desc *rx_descs;
23 struct msgdma_pref_extended_desc *tx_descs;
24 dma_addr_t rx_descsphys;
25 dma_addr_t tx_descsphys;
26
27 priv->pref_rxdescphys = (dma_addr_t)0;
28 priv->pref_txdescphys = (dma_addr_t)0;
29
30 /* we need to allocate more pref descriptors than ringsize to
31 * prevent all of the descriptors being owned by hw. To do this
32 * we just allocate twice ring_size descriptors.
33 * rx_ring_size = priv->rx_ring_size * 2
34 * tx_ring_size = priv->tx_ring_size * 2
35 */
36
37 /* The prefetcher requires the descriptors to be aligned to the
38 * descriptor read/write master's data width which worst case is
39 * 512 bits. Currently we DO NOT CHECK THIS and only support 32-bit
40 * prefetcher masters.
41 */
42
43 /* allocate memory for rx descriptors */
44 priv->pref_rxdesc =
45 dma_alloc_coherent(priv->device,
46 sizeof(struct msgdma_pref_extended_desc)
47 * priv->rx_ring_size * 2,
48 &priv->pref_rxdescphys, GFP_KERNEL);
49
50 if (!priv->pref_rxdesc)
51 goto err_rx;
52
53 /* allocate memory for tx descriptors */
54 priv->pref_txdesc =
55 dma_alloc_coherent(priv->device,
56 sizeof(struct msgdma_pref_extended_desc)
57 * priv->tx_ring_size * 2,
58 &priv->pref_txdescphys, GFP_KERNEL);
59
60 if (!priv->pref_txdesc)
61 goto err_tx;
62
63 /* setup base descriptor ring for tx & rx */
64 rx_descs = (struct msgdma_pref_extended_desc *)priv->pref_rxdesc;
65 tx_descs = (struct msgdma_pref_extended_desc *)priv->pref_txdesc;
66 tx_descsphys = priv->pref_txdescphys;
67 rx_descsphys = priv->pref_rxdescphys;
68
69 /* setup RX descriptors */
70 priv->pref_rx_prod = 0;
71 for (i = 0; i < priv->rx_ring_size * 2; i++) {
72 rx_descsphys = priv->pref_rxdescphys +
73 (((i + 1) % (priv->rx_ring_size * 2)) *
74 sizeof(struct msgdma_pref_extended_desc));
75 rx_descs[i].next_desc_lo = lower_32_bits(rx_descsphys);
76 rx_descs[i].next_desc_hi = upper_32_bits(rx_descsphys);
77 rx_descs[i].stride = MSGDMA_DESC_RX_STRIDE;
78 /* burst set to 0 so it defaults to max configured */
79 /* set seq number to desc number */
80 rx_descs[i].burst_seq_num = i;
81 }
82
83 /* setup TX descriptors */
84 for (i = 0; i < priv->tx_ring_size * 2; i++) {
85 tx_descsphys = priv->pref_txdescphys +
86 (((i + 1) % (priv->tx_ring_size * 2)) *
87 sizeof(struct msgdma_pref_extended_desc));
88 tx_descs[i].next_desc_lo = lower_32_bits(tx_descsphys);
89 tx_descs[i].next_desc_hi = upper_32_bits(tx_descsphys);
90 tx_descs[i].stride = MSGDMA_DESC_TX_STRIDE;
91 /* burst set to 0 so it defaults to max configured */
92 /* set seq number to desc number */
93 tx_descs[i].burst_seq_num = i;
94 }
95
96 if (netif_msg_ifup(priv))
> 97 netdev_info(priv->dev, "%s: RX Desc mem at 0x%x\n", __func__,
98 priv->pref_rxdescphys);
99
100 if (netif_msg_ifup(priv))
101 netdev_info(priv->dev, "%s: TX Desc mem at 0x%x\n", __func__,
102 priv->pref_txdescphys);
103
104 return 0;
105
106 err_tx:
107 dma_free_coherent(priv->device,
108 sizeof(struct msgdma_pref_extended_desc)
109 * priv->rx_ring_size * 2,
110 priv->pref_rxdesc, priv->pref_rxdescphys);
111 err_rx:
112 return -ENOMEM;
113 }
114
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Download attachment ".config.gz" of type "application/gzip" (63048 bytes)
Powered by blists - more mailing lists