netdev - Re: [PATCH net-next v3 5/8] net: phy: mscc: 1588 block initialization

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Date:   Sat, 20 Jun 2020 17:10:01 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Antoine Tenart <antoine.tenart@...tlin.com>
Cc:     davem@...emloft.net, f.fainelli@...il.com, hkallweit1@...il.com,
        richardcochran@...il.com, alexandre.belloni@...tlin.com,
        UNGLinuxDriver@...rochip.com, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, thomas.petazzoni@...tlin.com,
        allan.nielsen@...rochip.com, foss@...il.net
Subject: Re: [PATCH net-next v3 5/8] net: phy: mscc: 1588 block initialization

On Fri, Jun 19, 2020 at 02:22:57PM +0200, Antoine Tenart wrote:
> From: Quentin Schulz <quentin.schulz@...tlin.com>
> 
> This patch adds the first parts of the 1588 support in the MSCC PHY,
> with registers definition and the 1588 block initialization.
> 
> Those PHYs are distributed in hardware packages containing multiple
> times the PHY. The VSC8584 for example is composed of 4 PHYs. With
> hardware packages, parts of the logic is usually common and one of the
> PHY has to be used for some parts of the initialization. Following this
> logic, the 1588 blocks of those PHYs are shared between two PHYs and
> accessing the registers has to be done using the "base" PHY of the
> group. This is handled thanks to helpers in the PTP code (and locks).
> We also need the MDIO bus lock while performing a single read or write
> to the 1588 registers as the read/write are composed of multiple MDIO
> transactions (and we don't want other threads updating the page).

Locking sounds complex. I assume LOCKDEP was your friend in getting
this correct and deadlock free.

> +	/* For multiple port PHYs; the MDIO address of the base PHY in the
> +	 * pair of two PHYs that share a 1588 engine. PHY0 and PHY2 are coupled.
> +	 * PHY1 and PHY3 as well. PHY0 and PHY1 are base PHYs for their
> +	 * respective pair.

There are some evil hardware engineers out there :-(

It would be good it Richard gave this code a once over.

   Andrew