netdev - Re: [PATCH net-next 1/7] net: dsa: felix: stop writing to read-only fields in MII

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Message-ID: <20200625162820.GF1551@shell.armlinux.org.uk>
Date:   Thu, 25 Jun 2020 17:28:20 +0100
From:   Russell King - ARM Linux admin <linux@...linux.org.uk>
To:     Vladimir Oltean <olteanv@...il.com>
Cc:     davem@...emloft.net, netdev@...r.kernel.org, andrew@...n.ch,
        f.fainelli@...il.com, vivien.didelot@...il.com,
        claudiu.manoil@....com, alexandru.marginean@....com,
        ioana.ciornei@....com
Subject: Re: [PATCH net-next 1/7] net: dsa: felix: stop writing to read-only
 fields in MII_BMCR

On Thu, Jun 25, 2020 at 06:23:25PM +0300, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@....com>
> 
> It looks like BMCR_SPEED and BMCR_DUPLEX are read-only, since they are
> actually configured through the vendor-specific IF_MODE (0x14) register.
> So, don't perform bogus writes to these fields, giving the impression
> that those writes do something.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>

Is this patch really worth the churn?

If the bits are read-only, and are ones, writing ones back to them seems
at least to me to be the sane thing to be doing, rather than writing
zeros.  It isn't giving a false impression IMHO.

Also note that these are documented as being used in 1000base-X mode.

"Read only bit always set to '1' to indicate that the Core (when used
as 1000Base-X) only supports Full Duplex mode of operation and does not
support HalfDuplex. Note: the SGMII mode is controlled with register
IF_MODE."

"Read only bits that define that the Core only operates in Gigabit
mode(1000Base-X): Bit 13 set to '0', Bit 6 set to '1'. Note: the SGMII
speed is controlled with register IF_MODE."

So, I think definitely for the 2500BASE-X case (which is merely
1000BASE-X clocked 2.5x faster) we certainly want to keep writing
these settings correctly as if they were writable.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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