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Message-ID: <CAGngYiUEx98QUAHrzFNWzMr5+oPS4-7Nqq91JzhtzGUG7=kagQ@mail.gmail.com>
Date: Thu, 2 Jul 2020 20:50:59 -0400
From: Sven Van Asbroeck <thesven73@...il.com>
To: Fabio Estevam <festevam@...il.com>
Cc: Shawn Guo <shawnguo@...nel.org>, Fugang Duan <fugang.duan@....com>,
Rob Herring <robh+dt@...nel.org>,
"David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
netdev <netdev@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
NXP Linux Team <linux-imx@....com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 3/3] ARM: imx6plus: optionally enable internal routing
of clk_enet_ref
Hi Fabio,
On Thu, Jul 2, 2020 at 6:29 PM Fabio Estevam <festevam@...il.com> wrote:
>
> With the device tree approach, I think that a better place to touch
> GPR5 would be inside the fec driver.
>
Cool idea. I notice that the latest FEC driver (v5.8-rc3) accesses individual
bits inside the gpr (via fsl,stop-mode). So perhaps I can do the same here,
and populate that gpr node in imx6qp.dtsi - because it doesn't exist on other
SoCs.
> For the property name, what about fsl,txclk-from-pll?
Sounds good. Does anyone have more suggestions?
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