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Message-ID: <df4affe7-922c-968d-6aa9-b92072aade4f@gmail.com>
Date: Wed, 8 Jul 2020 13:03:58 +0300
From: Sergei Shtylyov <sergei.shtylyov@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
"David S . Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Rob Herring <robh+dt@...nel.org>
Cc: Andrew Lunn <andrew@...n.ch>,
Oleksij Rempel <linux@...pel-privat.de>,
Philippe Schenker <philippe.schenker@...adex.com>,
Florian Fainelli <f.fainelli@...il.com>,
Heiner Kallweit <hkallweit1@...il.com>,
Dan Murphy <dmurphy@...com>,
Kazuya Mizuguchi <kazuya.mizuguchi.ks@...esas.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Magnus Damm <magnus.damm@...il.com>, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v2 2/7] dt-bindings: net: renesas,ravb: Document internal
clock delay properties
Hello!
On 06.07.2020 17:35, Geert Uytterhoeven wrote:
> Some EtherAVB variants support internal clock delay configuration, which
> can add larger delays than the delays that are typically supported by
> the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> properties).
>
> Add properties for configuring the internal MAC delays.
> These properties are mandatory, even when specified as zero, to
> distinguish between old and new DTBs.
>
> Update the (bogus) example accordingly.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@...der.be>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
[...]
MBR, Sergei
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