netdev - [PATCH net 1/1] docs: ptp.rst: add support for Renesas (IDT) ClockMatrix

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Date:   Tue, 14 Jul 2020 13:15:20 -0400
From:   <min.li.xe@...esas.com>
To:     <richardcochran@...il.com>, <corbet@....net>
CC:     <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-doc@...r.kernel.org>, Min Li <min.li.xe@...esas.com>
Subject: [PATCH net 1/1] docs: ptp.rst: add support for Renesas (IDT) ClockMatrix

From: Min Li <min.li.xe@...esas.com>

Add below to “Ancillary clock features” section
  - Low Pass Filter (LPF) access from user space

Add below to list of “Supported hardware” section
  + Renesas (IDT) ClockMatrix™

Signed-off-by: Min Li <min.li.xe@...esas.com>
---
 Documentation/driver-api/ptp.rst | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/driver-api/ptp.rst b/Documentation/driver-api/ptp.rst
index a15192e..664838a 100644
--- a/Documentation/driver-api/ptp.rst
+++ b/Documentation/driver-api/ptp.rst
@@ -23,6 +23,7 @@ PTP hardware clock infrastructure for Linux
   + Ancillary clock features
     - Time stamp external events
     - Period output signals configurable from user space
+    - Low Pass Filter (LPF) access from user space
     - Synchronization of the Linux system time via the PPS subsystem
 
 PTP hardware clock kernel API
@@ -94,3 +95,14 @@ Supported hardware
 
      - Auxiliary Slave/Master Mode Snapshot (optional interrupt)
      - Target Time (optional interrupt)
+
+   * Renesas (IDT) ClockMatrix™
+
+     - Up to 4 independent PHC channels
+     - Integrated low pass filter (LPF), access via .adjPhase (compliant to ITU-T G.8273.2)
+     - Programmable output periodic signals
+     - Programmable inputs can time stamp external triggers
+     - Driver and/or hardware configuration through firmware (idtcm.bin)
+          - LPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2))
+          - Programmable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)
+          - Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional)
-- 
2.7.4