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Date: Sun, 16 Aug 2020 20:07:32 +0100 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> To: Geert Uytterhoeven <geert+renesas@...der.be>, Wolfgang Grandegger <wg@...ndegger.com>, Marc Kleine-Budde <mkl@...gutronix.de>, "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, Rob Herring <robh+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>, Linus Walleij <linus.walleij@...aro.org> Cc: linux-can@...r.kernel.org, netdev@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, linux-gpio@...r.kernel.org, Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, Prabhakar <prabhakar.csengg@...il.com> Subject: [PATCH 3/3] ARM: dts: r8a7742: Add CAN support Add the definitions for can0 and can1 to the r8a7742 SoC dtsi. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@...esas.com> --- arch/arm/boot/dts/r8a7742.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 009827708bf4..0fc52b27ae64 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -36,6 +36,14 @@ clock-frequency = <0>; }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -951,6 +959,32 @@ status = "disabled"; }; + can0: can@...80000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@...88000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + pwm0: pwm@...30000 { compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; -- 2.17.1
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