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Date:   Mon, 24 Aug 2020 10:56:13 -0700
From:   Florian Fainelli <>
To:     Geert Uytterhoeven <>,
        "David S . Miller" <>,
        Jakub Kicinski <>,
        Rob Herring <>,
        Sergei Shtylyov <>
Cc:     Andrew Lunn <>,
        Oleksij Rempel <>,
        Philippe Schenker <>,
        Heiner Kallweit <>,
        Dan Murphy <>,
        Kazuya Mizuguchi <>,
        Wolfram Sang <>,
        Magnus Damm <>,,,,
Subject: Re: [PATCH v3 2/7] dt-bindings: net: renesas,ravb: Document internal
 clock delay properties

On 8/19/20 6:43 AM, Geert Uytterhoeven wrote:
> Some EtherAVB variants support internal clock delay configuration, which
> can add larger delays than the delays that are typically supported by
> the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps"
> properties).
> Add properties for configuring the internal MAC delays.
> These properties are mandatory, even when specified as zero, to
> distinguish between old and new DTBs.
> Update the (bogus) example accordingly.
> Signed-off-by: Geert Uytterhoeven <>
> Reviewed-by: Sergei Shtylyov <>
> Reviewed-by: Rob Herring <>

Reviewed-by: Florian Fainelli <>

Is there a plan to convert renesas,ravb.txt to a YAML binding?

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