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Date:   Tue, 25 Aug 2020 06:22:25 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     daniel.gorsulowski@....eu
Cc:     netdev@...r.kernel.org, andrew@...n.ch, f.fainelli@...il.com,
        hkallweit1@...il.com
Subject: Re: [PATCH] net: dp83869: Fix RGMII internal delay configuration

From: Daniel Gorsulowski <daniel.gorsulowski@....eu>
Date: Tue, 25 Aug 2020 14:07:21 +0200

> The RGMII control register at 0x32 indicates the states for the bits
> RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:
> 
>   RGMII Transmit/Receive Clock Delay
>     0x0 = RGMII transmit clock is shifted with respect to transmit/receive data.
>     0x1 = RGMII transmit clock is aligned with respect to transmit/receive data.
> 
> This commit fixes the inversed behavior of these bits
> 
> Fixes: 736b25afe284 ("net: dp83869: Add RGMII internal delay configuration")
> 
> Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@....eu>

Please no empty lines between "Fixes:" and other tags like "Signed-off-by:",
all of the tags should be grouped together without any intervening empty
lines.

> -		val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
> +		val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
>  			 DP83869_RGMII_RX_CLK_DELAY_EN);

Please fix up the indentation of this last line here such that the
first character is at the same column as the one after the openning
parenthesis of the previous line.

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