netdev - Re: drivers/of/of_mdio.c needs a small modification

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20200829151553.GB2912863@lunn.ch>
Date:   Sat, 29 Aug 2020 17:15:53 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Adam Rudziński <adam.rudzinski@....net.pl>
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        netdev <netdev@...r.kernel.org>, robh+dt@...nel.org,
        frowand.list@...il.com
Subject: Re: drivers/of/of_mdio.c needs a small modification

> The driver would be able to add the new PHYs to the shared MDIO bus by
> calling of_mdiobus_register_children. Then the device tree looks like this,
> which is more reasonable in my opinion:
> 
> &fec2 {
> (...)
>     mdio {
>         (phy for fec2 here)
>     };
> (...)
> };
> 
> &fec1 {
> (...)
>     mdio {
>         (phy for fec1 here)
>     };
> (...)
> };

DT describes hardware, and the topology of the hardware. The hardware really is:

ethernet1@...ec000 {
	compatible = "fsl,imx51-fec", "fsl,imx27-fec";
	reg = <0x83fec000 0x4000>;
	interrupts = <87>;
	phy-mode = "mii";
	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; /* GPIO2_14 */
	local-mac-address = [00 04 9F 01 1B B9];
	phy-supply = <&reg_fec_supply>;
	phy-handle = <&ethphy1>;
	mdio {
	        clock-frequency = <5000000>;
		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			max-speed = <100>;
		};
		ethphy2: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <2>;
			max-speed = <100>;
		};
	};
};

ethernet2@...ec000 {
	compatible = "fsl,imx51-fec", "fsl,imx27-fec";
	reg = <0x83fec000 0x4000>;
	interrupts = <87>;
	phy-mode = "mii";
	phy-reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* GPIO2_15 */
	local-mac-address = [00 04 9F 01 1B BA];
	phy-supply = <&reg_fec_supply>;
	phy-handle = <&ethphy2>;
};

What is missing from this is clocks. The IMX has a central clock
provider:

                        clks: clock-controller@...4000 {
                                compatible = "fsl,imx6ul-ccm";
                                reg = <0x020c4000 0x4000>;
                                interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
                                #clock-cells = <1>;
                                clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
                                clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
                        };

and it exports two clocks, MX6UL_CLK_ENET1_REF, MX6UL_CLK_ENET2_REF

So adding the clock properties:

ethernet1@...ec000 {
	compatible = "fsl,imx51-fec", "fsl,imx27-fec";
	reg = <0x83fec000 0x4000>;
	interrupts = <87>;
	phy-mode = "mii";
	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; /* GPIO2_14 */
	local-mac-address = [00 04 9F 01 1B B9];
	phy-supply = <&reg_fec_supply>;
	phy-handle = <&ethphy1>;
	mdio {
	        clock-frequency = <5000000>;
		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			max-speed = <100>;
			clocks = <&clks MX6UL_CLK_ENET1_REF>;
		};
		ethphy2: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <2>;
			max-speed = <100>;
			clocks = <&clks MX6UL_CLK_ENET2_REF>;
		};
	};
};

ethernet2@...ec000 {
	compatible = "fsl,imx51-fec", "fsl,imx27-fec";
	reg = <0x83fec000 0x4000>;
	interrupts = <87>;
	phy-mode = "mii";
	phy-reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* GPIO2_15 */
	local-mac-address = [00 04 9F 01 1B BA];
	phy-supply = <&reg_fec_supply>;
	phy-handle = <&ethphy2>;
};

Also look at drivers/net/phy/micrel.c. It has code to look up a FEC
clock and use it. But that code assumes the PHY responds to MDIO reads
when the clock is not ticking. It sounds like your PHY does not?
Please double check that. If it does not, you need to add clock code
to the PHY core. Florians patchset will help with that.

	Andrew