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Date:   Wed, 2 Sep 2020 18:54:30 -0700
From:   Florian Fainelli <>
To:     Andrew Lunn <>
Cc:, Vivien Didelot <>,
        "David S. Miller" <>,
        Jakub Kicinski <>,
        open list <>
Subject: Re: [PATCH net-next] net: dsa: bcm_sf2: Ensure that MDIO diversion is

On 9/2/2020 6:13 PM, Andrew Lunn wrote:
> On Wed, Sep 02, 2020 at 02:03:27PM -0700, Florian Fainelli wrote:
>> Registering our slave MDIO bus outside of the OF infrastructure is
>> necessary in order to avoid creating double references of the same
>> Device Tree nodes, however it is not sufficient to guarantee that the
>> MDIO bus diversion is used because of_phy_connect() will still resolve
>> to a valid PHY phandle and it will connect to the PHY using its parent
>> MDIO bus which is still the SF2 master MDIO bus.
>> Ensure that of_phy_connect() does not suceed by removing any phandle
>> reference for the PHY we need to divert. This forces the DSA code to use
>> the DSA slave_mii_bus that we register and ensures the MDIO diversion is
>> being used.
> Hi Florian
> Sorry, i don't get this explanation. Can you point me towards a device
> tree i can look at to maybe understand what is going on.
The firmware provides the Device Tree but here is the relevant section 
for you pasted below. The problematic device is a particular revision of 
the silicon (D0) which got later fixed (E0) however the Device Tree was 
created after the fixed platform, not the problematic one. Both 
revisions of the silicon are in production.

There should have been an internal MDIO bus created for that chip 
revision such that we could have correctly parented phy@0 (bcm53125 
below) as child node of the internal MDIO bus, but you have to realize 
that this was done back in 2014 when DSA was barely revived as an active 
subsystem. The BCM53125 node should have have been converted to an 
actual switch node at some point, I use a mdio_boardinfo overlay 
downstream to support the switch as a proper b53/DSA switch, anyway.

The problem is that of_phy_connect() for port@1 will resolve the 
phy-handle from the mdio@...c0 node, which bypasses the diversion 
completely. This results in this double programming that the diversion 
refers to. In order to force of_phy_connect() to fail, and have DSA call 
to dsa_slave_phy_connect(), we must deactivate ethernet-phy@0 from 
mdio@...c0, and the best way to do that is by removing the phandle 
property completely.

Hope this clarifies the mess :)

		switch_top@...00000 {
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			compatible = "brcm,bcm7445-switch-top-v2.0\0simple-bus";
			ranges = <0x00 0xf0b00000 0x40804>;

			ethernet_switch@0 {
				#address-cells = <0x02>;
				#size-cells = <0x00>;
				brcm,num-acb-queues = <0x40>;
				brcm,num-gphy = <0x01>;
				brcm,num-rgmii-ports = <0x02>;
				compatible = "brcm,bcm7445-switch-v4.0\0brcm,bcm53012";
				dsa,ethernet = <0x16>;
				dsa,mii-bus = <0x17>;
				resets = <0x18 0x1a>;
				reset-names = "switch";
				reg = <0x00 0x40000 0x40000 0x110 0x40340 0x30 0x40380 0x30 0x40400 
0x34 0x40600 0x208>;
				reg-names = "core\0reg\0intrl2_0\0intrl2_1\0fcb\0acb";
				interrupts = <0x00 0x18 0x04 0x00 0x19 0x04>;
				interrupt-names = "switch_0\0switch_1";
				clocks = <0x0a 0x6d 0x0a 0x76>;
				clock-names = "sw_switch\0sw_switch_mdiv";

				ports {
					#address-cells = <0x01>;
					#size-cells = <0x00>;

					port@0 {
						phy-mode = "internal";
						phy-handle = <0x29>;
						linux,phandle = <0x2a>;
						phandle = <0x2a>;
						reg = <0x00>;
						label = "gphy";

					port@1 {
						phy-mode = "rgmii-txid";
						phy-handle = <0x2c>;
						linux,phandle = <0x2d>;
						phandle = <0x2d>;
						reg = <0x01>;
						label = "rgmii_1";

					port@2 {
						phy-mode = "rgmii-txid";
						fixed-link = <0x02 0x01 0x3e8 0x00 0x00>;
						linux,phandle = <0x2f>;
						phandle = <0x2f>;
						reg = <0x02>;
						label = "rgmii_2";

					port@7 {
						phy-mode = "moca";
						fixed-link = <0x07 0x01 0x3e8 0x00 0x00>;
						linux,phandle = <0x31>;
						phandle = <0x31>;
						reg = <0x07>;
						label = "moca";

					port@8 {
						linux,phandle = <0x33>;
						phandle = <0x33>;
						reg = <0x08>;
						label = "cpu";
						ethernet = <0x16>;

			mdio@...c0 {
				reg = <0x403c0 0x08 0x40300 0x18>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				compatible = "brcm,bcm7445-mdio-v4.0\0brcm,unimac-mdio";
				reg-names = "mdio\0mdio_indir_rw";
				clocks = <0x0a 0x6d>;
				clock-names = "sw_switch";
				linux,phandle = <0x17>;
				phandle = <0x17>;

				ethernet-phy@0 {
					linux,phandle = <0x2c>;
					phandle = <0x2c>;
					device_type = "ethernet-phy";
					max-speed = <0x3e8>;
					reg = <0x00>;
					compatible = "brcm,bcm53125\0ethernet-phy-ieee802.3-c22";

				ethernet-phy@5 {
					linux,phandle = <0x29>;
					phandle = <0x29>;
					clock-names = "sw_gphy";
					clocks = <0x0a 0x63>;
					device_type = "ethernet-phy";
					max-speed = <0x3e8>;
					reg = <0x05>;
					compatible = "brcm,28nm-gphy\0ethernet-phy-ieee802.3-c22";

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