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Message-ID: <BYAPR18MB2791A52DA3BF1D7BE5574F99A02D0@BYAPR18MB2791.namprd18.prod.outlook.com>
Date:   Fri, 4 Sep 2020 14:14:34 +0000
From:   Srujana Challa <schalla@...vell.com>
To:     Herbert Xu <herbert@...dor.apana.org.au>
CC:     "davem@...emloft.net" <davem@...emloft.net>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
        Suheil Chandran <schandran@...vell.com>,
        Narayana Prasad Raju Athreya <pathreya@...vell.com>,
        Sunil Kovvuri Goutham <sgoutham@...vell.com>,
        Linu Cherian <lcherian@...vell.com>,
        "Geethasowjanya Akula" <gakula@...vell.com>,
        Jerin Jacob Kollanukkaran <jerinj@...vell.com>,
        Ard Biesheuvel <ardb@...nel.org>
Subject: RE: [EXT] Re: [PATCH v2 2/3] drivers: crypto: add support for
 OCTEONTX2 CPT engine

> Subject: [EXT] Re: [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2
> CPT engine
> 
> External Email
> 
> ----------------------------------------------------------------------
> On Fri, Sep 04, 2020 at 01:45:38PM +0000, Srujana Challa wrote:
> >
> > This block of code is used for LMT store operations. The LMT store operation
> > is specific to our platform, and this uses the "ldeor" instruction(which is
> > actually an LSE atomic instruction available on v8.1 CPUs) targeting the
> > IO address.
> > We add it in the driver since we want LMT store to work even if LSE_ATOMICS
> > is disabled.
> 
> You have exactly the same macro in your net driver.  Move it into
> a header file in arch/arm64/include/asm and also add one under
> include/asm-generic so we can compile-test.
>
Since LMT store is our platform specific, it cannot be generalized to all ARM64.

> Thanks,
> --
> Email: Herbert Xu <herbert@...dor.apana.org.au>
> Home Page: https://urldefense.proofpoint.com/v2/url?u=http-
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