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Date:   Fri, 4 Sep 2020 21:23:26 +0200
From:   Marek Vasut <marex@...x.de>
To:     Richard Leitner <richard.leitner@...data.com>
Cc:     Andrew Lunn <andrew@...n.ch>, netdev@...r.kernel.org,
        Christoph Niedermaier <cniedermaier@...electronics.com>,
        "David S . Miller" <davem@...emloft.net>,
        NXP Linux Team <linux-imx@....com>,
        Shawn Guo <shawnguo@...nel.org>
Subject: Re: [PATCH] net: fec: Fix PHY init after phy_reset_after_clk_enable()

On 9/4/20 9:02 PM, Richard Leitner wrote:
> On Fri, Sep 04, 2020 at 05:26:14PM +0200, Marek Vasut wrote:
>> On 9/4/20 4:02 PM, Andrew Lunn wrote:
>>> On Fri, Sep 04, 2020 at 12:45:44AM +0200, Marek Vasut wrote:
>>>> On 9/4/20 12:08 AM, Andrew Lunn wrote:
>>>>>>> b4 am 20200903043947.3272453-1-f.fainelli@...il.com
>>>>>>
>>>>>> That might be a fix for the long run, but I doubt there's any chance to
>>>>>> backport it all to stable, is there ?
>>>>>
>>>>> No. For stable we need something simpler.
>>>>
>>>> Like this patch ?
>>>
>>> Yes.
>>>
>>> But i would like to see a Tested-By: or similar from Richard
>>> Leitner. Why does the current code work for his system? Does your
>>> change break it?
>>
>> I have the IRQ line connected and described in DT. The reset clears the
>> IRQ settings done by the SMSC PHY driver. The PHY works fine if I use
>> polling, because then even if no IRQs are generated by the PHY, the PHY
>> framework reads the status updates from the PHY periodically and the
>> default settings of the PHY somehow work (even if they are slightly
>> incorrect). I suspect that's how Richard had it working.
> 
> I have different PHYs on different PCBs in use, but IIRC none of them
> has the IRQ line defined in the DT.
> I will take a look at it, test your patch and give feedback ASAP.
> Unfortunately it's unlikely that this will be before monday 😕
> Hope that's ok.

That's totally fine, thanks !

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