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Date:   Fri, 4 Sep 2020 08:26:47 +0100
From:   Russell King - ARM Linux admin <>
To:     Andrew Lunn <>
Cc:     Alexandre Belloni <>,
        Antoine Tenart <>,
        Richard Cochran <>,
        Matteo Croce <>,
        Andre Przywara <>,
        Sven Auhagen <>,
        "David S. Miller" <>,
        Jakub Kicinski <>,
Subject: Re: [PATCH net-next 3/7] net: mvpp2: check first level interrupt
 status registers

On Thu, Sep 03, 2020 at 03:24:14AM +0200, Andrew Lunn wrote:
> On Wed, Sep 02, 2020 at 05:11:46PM +0100, Russell King wrote:
> > Check the first level interrupt status registers to determine how to
> > further process the port interrupt. We will need this to know whether
> > to invoke the link status processing and/or the PTP processing for
> > both XLG and GMAC.
> As i said, i don't know this driver. Does the hardware actually have
> two MAC hardware blocks? One for 10Mbs->1G, and a second for > 1G?


RMK's Patch system:
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

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