netdev - Re: [PATCH net-next 3/7] net: mvpp2: check first level interrupt status registers

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Message-ID: <20200904072646.GP1551@shell.armlinux.org.uk>
Date:   Fri, 4 Sep 2020 08:26:47 +0100
From:   Russell King - ARM Linux admin <linux@...linux.org.uk>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Antoine Tenart <antoine.tenart@...tlin.com>,
        Richard Cochran <richardcochran@...il.com>,
        Matteo Croce <mcroce@...hat.com>,
        Andre Przywara <andre.przywara@....com>,
        Sven Auhagen <sven.auhagen@...eatech.de>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org
Subject: Re: [PATCH net-next 3/7] net: mvpp2: check first level interrupt
 status registers

On Thu, Sep 03, 2020 at 03:24:14AM +0200, Andrew Lunn wrote:
> On Wed, Sep 02, 2020 at 05:11:46PM +0100, Russell King wrote:
> > Check the first level interrupt status registers to determine how to
> > further process the port interrupt. We will need this to know whether
> > to invoke the link status processing and/or the PTP processing for
> > both XLG and GMAC.
> 
> As i said, i don't know this driver. Does the hardware actually have
> two MAC hardware blocks? One for 10Mbs->1G, and a second for > 1G?

Yes.

-- 
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