netdev - Re: [PATCH] net: phy: realtek: fix rtl8211e rx/tx delay config

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20200918153301.chwlvzh6a2bctbjw@mobilestation>
Date:   Fri, 18 Sep 2020 18:33:01 +0300
From:   Serge Semin <fancer.lancer@...il.com>
To:     Andrew Lunn <andrew@...n.ch>, Kyle Evans <kevans@...eBSD.org>,
        Willy Liu <willy.liu@...ltek.com>
Cc:     "hkallweit1@...il.com" <hkallweit1@...il.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Ryan Kao <ryankao@...ltek.com>,
        Joe Hershberger <joe.hershberger@...com>,
        Peter Robinson <pbrobinson@...il.com>
Subject: Re: [PATCH] net: phy: realtek: fix rtl8211e rx/tx delay config

Hello Andrew.

On Fri, Sep 18, 2020 at 03:54:03PM +0200, Andrew Lunn wrote:
> On Fri, Sep 18, 2020 at 06:55:16AM +0000, 劉偉權 wrote:
> > Hi Serge,
> 
> > Thanks for your reply. There is a confidential issue that realtek
> > doesn't offer the detail of a full register layout for configuration
> > register.
> 
> ...
> 
> > >  	 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
> > >  	 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
> > >  	 * also be used to customize the whole configuration register:
> > 
> > > -	 * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
> > > -	 * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
> > > -	 * for details).
> > > +	 * 13 = Force Tx RX Delay controlled by bit12 bit11,
> > > +	 * 12 = RX Delay, 11 = TX Delay
> > 
> 
> > Here you've removed the register layout description and replaced itq
> > with just three bits info. So from now the text above doesn't really
> > corresponds to what follows.
> 
> > I might have forgotten something, but AFAIR that register bits
> > stateq mapped well to what was available on the corresponding
> > external pins.
> 
> Hi Willy
> 

> So it appears bits 3 to 8 have been reverse engineered. Unless you
> know from your confidential datasheet that these are wrong, please
> leave the comment alone.
> 
> If you confidential datasheet says that the usage of bits 0-2 is
> wrong, then please do correct that part.

I've got that info from Kyle post here:
https://reviews.freebsd.org/D13591

My work with that problem has been done more than a year ago, so I don't
remember all the details. But IIRC the very first nine bits [8:0] must be a copy
of what is set on the external configuration pins as I described in the comment.
AFAIR I tried to manually change these pins [1] and detected that change right
there in the register. That fully fitted to what Kyle wrote in his post. Alas I
can't repeat it to be completely sure at the moment due to the lack of the
hardware. So I might have missed something, and Willy' confirmation about that
would have been more than welcome. What we can say now for sure I didn't use
the magic number in my patch. That could have been a mistake from what Willy
says in the commit-log...

Anyway aside with the Magic bits settings (which by Willy' patch appears to be
the Tx/Rx delays + Force Tx/Rx delay setting) Kyle also clears the bits 1-2 with
a comment "Ensure both internal delays are turned off". Willy, what can you say
about that? Can we really leave them out from the change? Kyle, could you give
us a comment about your experience with that?

[1] RTL8211E-VB-CG, RTL8211E-VL-CG, RTL8211E-VL-CG, "INTEGRATED 10/100/1000M ETHERNET
    TRANSCEIVER" Datasheet, Table 13. Configuration Register Definition, Rev. 1.6,
    03 April 2012, Track ID: JATR-3375-16, p.16

-Sergey

> 
>        Andrew