netdev - Re: [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 24 Sep 2020 09:08:16 +0200
From:   Alexandre Belloni <alexandre.belloni@...tlin.com>
To:     Xiaoliang Yang <xiaoliang.yang_1@....com>
Cc:     davem@...emloft.net, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, allan.nielsen@...rochip.com,
        joergen.andreasen@...rochip.com, UNGLinuxDriver@...rochip.com,
        fido_max@...ox.ru, alexandru.marginean@....com, po.liu@....com,
        claudiu.manoil@....com, vladimir.oltean@....com, leoyang.li@....com
Subject: Re: [net] net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3

Hi,

On 24/09/2020 10:11:13+0800, Xiaoliang Yang wrote:
> INIT_IPS and GATE_ENABLE fields have a wrong offset in SG_CONFIG_REG_3.

You are changing GATE_STATE, not GATE_ENABLE

> This register is used by stream gate control of PSFP, and it has not
> been used before, because PSFP is not implemented in ocelot driver.
> 
> Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@....com>
> ---
>  include/soc/mscc/ocelot_ana.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/soc/mscc/ocelot_ana.h b/include/soc/mscc/ocelot_ana.h
> index 841c6ec22b64..1669481d9779 100644
> --- a/include/soc/mscc/ocelot_ana.h
> +++ b/include/soc/mscc/ocelot_ana.h
> @@ -252,10 +252,10 @@
>  #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M                 GENMASK(18, 16)
>  #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x)              (((x) & GENMASK(18, 16)) >> 16)
>  #define ANA_SG_CONFIG_REG_3_GATE_ENABLE                   BIT(20)
> -#define ANA_SG_CONFIG_REG_3_INIT_IPS(x)                   (((x) << 24) & GENMASK(27, 24))
> -#define ANA_SG_CONFIG_REG_3_INIT_IPS_M                    GENMASK(27, 24)
> -#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x)                 (((x) & GENMASK(27, 24)) >> 24)
> -#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE               BIT(28)
> +#define ANA_SG_CONFIG_REG_3_INIT_IPS(x)                   (((x) << 21) & GENMASK(24, 21))
> +#define ANA_SG_CONFIG_REG_3_INIT_IPS_M                    GENMASK(24, 21)
> +#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x)                 (((x) & GENMASK(24, 21)) >> 21)
> +#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE               BIT(25)
>  

VSC7514 doesn't have the stream gate registers ans this was generated
automatically from the cml file for felix. Did that change?

Seeing that bits in this register are not packed, I would believe your
change is correct.

>  #define ANA_SG_GCL_GS_CONFIG_RSZ                          0x4
>  
> -- 
> 2.17.1
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com