netdev - Re: RGMII timing calibration (on 12nm Amlogic SoCs)

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Date:   Sat, 26 Sep 2020 00:14:03 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc:     netdev@...r.kernel.org, linux-amlogic@...ts.infradead.org,
        alexandre.torgue@...com, linux-kernel@...r.kernel.org,
        linux@...linux.org.uk, joabreu@...opsys.com, kuba@...nel.org,
        peppe.cavallaro@...com, davem@...emloft.net,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: RGMII timing calibration (on 12nm Amlogic SoCs) - integration
 into dwmac-meson8b

On Fri, Sep 25, 2020 at 11:47:18PM +0200, Martin Blumenstingl wrote:
> Hello,
> 
> Amlogic's 12nm SoC generation requires some RGMII timing calibration
> within the Ethernet controller glue registers.
> This calibration is only needed for the RGMII modes, not for the
> (internal) RMII PHY.
> With "incorrect" calibration settings Ethernet speeds up to 100Mbit/s
> will still work fine, but no data is flowing on 1Gbit/s connections
> (similar to when RX or TX delay settings are incorrect).

Hi Martin

Is this trying to detect the correct RGMII interface mode:
        PHY_INTERFACE_MODE_RGMII,
        PHY_INTERFACE_MODE_RGMII_ID,
        PHY_INTERFACE_MODE_RGMII_RXID,
        PHY_INTERFACE_MODE_RGMII_TXID,

In general, we recommend the MAC does not insert any delay, we leave
it up to the PHY. In DT, you then set the correct phy-mode value,
which gets passed to the PHY when the MAC calls the connect function.

Is there any documentation as to what the calibration values mean?  I
would just hard code it to whatever means 0uS delay, and be done. The
only time the MAC needs to add delays is when the PHY is not capable
of doing it, and generally, they all are.

      Andrew