lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 26 Sep 2020 16:45:13 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc:     netdev@...r.kernel.org, linux-amlogic@...ts.infradead.org,
        alexandre.torgue@...com, linux-kernel@...r.kernel.org,
        linux@...linux.org.uk, joabreu@...opsys.com, kuba@...nel.org,
        peppe.cavallaro@...com, davem@...emloft.net,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: RGMII timing calibration (on 12nm Amlogic SoCs) - integration
 into dwmac-meson8b

> I checked this again for the vendor u-boot (where Ethernet is NOT
> working) as well as the Android kernel which this board was shipped
> with (where Ethernet is working)
> - in u-boot the MAC side adds a 2ns TX delay and the PHY side adds a
> 2ns RX delay

So that suggest there is nothing on the PCB. It is all down to MAC and
PHY adding delays.

> yes, there's only one calibration value
> the reference code is calculating the calibration setting for four
> configuration variants:
> - 2ns TX delay on the MAC side, no RX or TX delay on the PHY side, RGMII RX_CLK not inverted
> - 2ns TX delay on the MAC side, no RX or TX delay on the PHY side, RGMII RX_CLK inverted
> - 2ns TX delay on the MAC side, 2ns RX delay on the PHY side, RGMII RX_CLK not inverted
> - 2ns TX delay on the MAC side, 2ns RX delay on the PHY side, RGMII RX_CLK inverted
> 
> now that I'm writing this, could it be a calibration of the RX_CLK
> signal?

Yes, seems like it. Which of these four does it end up using? I'm
guessing the 3rd?

So i would forget about configuration clock inversion. Hard code it to
whatever works. It is not something you see other MAC/PHY combinations
allow to configure.

I think you said a value of 0x2 works. I wonder if that corresponds to
something slightly larger than 0ns if option 3 is being used?

> In the meantime Amlogic's "hacked" PHY driver is also using these registers: [0]
> So I assume that I'm doing the right thing in the Realtek PHY driver

Thanks for confirming this. No need to check for the resistors.

       Andrew

Powered by blists - more mailing lists