netdev - Re: [PATCH 2/2] net: dsa: mv88e6xxx: Support serdes ports on MV88E6097

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <7ccfd1d2-cf03-9eca-a3d6-c68267d08f76@alliedtelesis.co.nz>
Date:   Mon, 19 Oct 2020 02:45:25 +0000
From:   Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "vivien.didelot@...il.com" <vivien.didelot@...il.com>,
        "f.fainelli@...il.com" <f.fainelli@...il.com>,
        "olteanv@...il.com" <olteanv@...il.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] net: dsa: mv88e6xxx: Support serdes ports on
 MV88E6097


On 19/10/20 11:31 am, Chris Packham wrote:
>
> On 19/10/20 11:08 am, Andrew Lunn wrote:
>> On Sun, Oct 18, 2020 at 09:15:52PM +0000, Chris Packham wrote:
>>> On 19/10/20 9:25 am, Andrew Lunn wrote:
>>>>> I assume you're talking about the PHY Control Register 0 bit 11. 
>>>>> If so
>>>>> that's for the internal PHYs on ports 0-7. Ports 8, 9 and 10 don't 
>>>>> have
>>>>> PHYs.
>>>> Hi Chris
>>>>
>>>> I have a datasheet for the 6122/6121, from some corner of the web,
>>>> Part 3 of 3, Gigabit PHYs and SERDES.
>>>>
>>>> http://www.image.micros.com.pl/_dane_techniczne_auto/ui88e6122b2lkj1i0.pdf 
>>>>
>>>>
>>>> Section 5 of this document talks
>>>> about the SERDES registers. Register 0 is Control, register 1 is
>>>> Status - Fiber, register 2 and 3 are the usual ID, 4 is auto-net
>>>> advertisement etc.
>>>>
>>>> Where these registers appear in the address space is not clear from
>>>> this document. It is normally in document part 2 of 3, which my
>>>> searching of the web did not find.
>>>>
>>>>       Andrew
>>> I have got the 88E6122 datasheet(s) and can see the SERDES registers
>>> you're talking about (I think they're in the same register space as the
>>> built-in PHYs). It looks like the 88E6097 is different in that there 
>>> are
>>> no SERDES registers exposed (at least not in a documented way). Looking
>>> at the 88E6185 it's the same as the 88E6097.
>> Hi Chris
>>
>> I find it odd there are no SERDES registers.  Can you poke around the
>> register space and look for ID registers? See if there are any with
>> Marvells OUI, but different to the chip ID found in the port
>> registers?
> From my experience with Marvell I don't think it's that odd. 
> Particularly for a 1G SERDES there's really not much that needs 
> configuring (although power up/down would be nice). I'll poke around 
> that register space to see if anything is there.

I poked around what I thought would be the relevant register space and 
couldn't find anything responding to the reads.

>>> So how do you want to move this series forward? I can test it on the
>>> 88E6097 (and have restricted it to just that chip for now), I'm pretty
>>> sure it'll work on the 88E6185. I doubt it'll work on the 88E6122 but
>>> maybe it would with a different serdes_power function (or even the
>>> mv88e6352_serdes_power() as you suggested).
>> Make your best guess for what you cannot test.
> Will do. I'll expand out at least to cover the 88E6185 in v2. I can 
> probably guess at the 88E6122 aside from the ability to power up/down 
> the rest looks the same from glancing the datasheets.