| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <afbabf3c247d311e18701b301d32b49919b34017.camel@calian.com>
Date: Mon, 26 Oct 2020 19:44:48 +0000
From: Robert Hancock <robert.hancock@...ian.com>
To: "radheys@...inx.com" <radheys@...inx.com>,
"davem@...emloft.net" <davem@...emloft.net>,
"kuba@...nel.org" <kuba@...nel.org>
CC: "linux@...linux.org.uk" <linux@...linux.org.uk>,
"michals@...inx.com" <michals@...inx.com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"andrew@...n.ch" <andrew@...n.ch>
Subject: Re: [PATCH net-next v2] net: axienet: Properly handle PCS/PMA PHY for
1000BaseX mode
On Mon, 2020-10-26 at 18:57 +0000, Radhey Shyam Pandey wrote:
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Robert Hancock <robert.hancock@...ian.com>
> > Sent: Monday, October 26, 2020 11:26 PM
> > To: Radhey Shyam Pandey <radheys@...inx.com>; davem@...emloft.net;
> > kuba@...nel.org
> > Cc: Michal Simek <michals@...inx.com>; linux@...linux.org.uk;
> > andrew@...n.ch; netdev@...r.kernel.org; Robert Hancock
> > <robert.hancock@...ian.com>
> > Subject: [PATCH net-next v2] net: axienet: Properly handle PCS/PMA
> > PHY for
> > 1000BaseX mode
> >
> > Update the axienet driver to properly support the Xilinx PCS/PMA
> > PHY
> > component which is used for 1000BaseX and SGMII modes, including
> > properly configuring the auto-negotiation mode of the PHY and
> > reading
> > the negotiated state from the PHY.
> >
> > Signed-off-by: Robert Hancock <robert.hancock@...ian.com>
> > ---
> >
> > Resubmit of v2 tagged for net-next.
> >
> > drivers/net/ethernet/xilinx/xilinx_axienet.h | 3 +
> > .../net/ethernet/xilinx/xilinx_axienet_main.c | 96 ++++++++++++++-
> > ----
> > 2 files changed, 73 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h
> > b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> > index f34c7903ff52..7326ad4d5e1c 100644
> > --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
> > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> > @@ -419,6 +419,9 @@ struct axienet_local {
> > struct phylink *phylink;
> > struct phylink_config phylink_config;
> >
> > + /* Reference to PCS/PMA PHY if used */
> > + struct mdio_device *pcs_phy;
> > +
> > /* Clock for AXI bus */
> > struct clk *clk;
> >
> > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> > b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> > index 9aafd3ecdaa4..f46595ef2822 100644
> > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> > @@ -1517,10 +1517,29 @@ static void axienet_validate(struct
> > phylink_config *config,
> >
> > phylink_set(mask, Asym_Pause);
> > phylink_set(mask, Pause);
> > - phylink_set(mask, 1000baseX_Full);
> > - phylink_set(mask, 10baseT_Full);
> > - phylink_set(mask, 100baseT_Full);
> > - phylink_set(mask, 1000baseT_Full);
> > +
> > + switch (state->interface) {
> > + case PHY_INTERFACE_MODE_NA:
> > + case PHY_INTERFACE_MODE_1000BASEX:
> > + case PHY_INTERFACE_MODE_SGMII:
> > + case PHY_INTERFACE_MODE_GMII:
> > + case PHY_INTERFACE_MODE_RGMII:
> > + case PHY_INTERFACE_MODE_RGMII_ID:
> > + case PHY_INTERFACE_MODE_RGMII_RXID:
> > + case PHY_INTERFACE_MODE_RGMII_TXID:
> > + phylink_set(mask, 1000baseX_Full);
> > + phylink_set(mask, 1000baseT_Full);
> > + if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
> > + break;
>
> 100BaseT and 10BaseT can be set in PHY_INTERFACE_MODE_MII if we
> allow fallthrough here.
Not quite sure what you are saying here?
> > + phylink_set(mask, 100baseT_Full);
> > + phylink_set(mask, 10baseT_Full);
> > + break;
> > + case PHY_INTERFACE_MODE_MII:
> > + phylink_set(mask, 100baseT_Full);
> > + phylink_set(mask, 10baseT_Full);
> > + default:
> > + break;
> > + }
> >
> > bitmap_and(supported, supported, mask,
> > __ETHTOOL_LINK_MODE_MASK_NBITS);
> > @@ -1533,38 +1552,46 @@ static void
> > axienet_mac_pcs_get_state(struct
> > phylink_config *config,
> > {
> > struct net_device *ndev = to_net_dev(config->dev);
> > struct axienet_local *lp = netdev_priv(ndev);
> > - u32 emmc_reg, fcc_reg;
> > -
> > - state->interface = lp->phy_mode;
> >
> > - emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
> > - if (emmc_reg & XAE_EMMC_LINKSPD_1000)
> > - state->speed = SPEED_1000;
> > - else if (emmc_reg & XAE_EMMC_LINKSPD_100)
> > - state->speed = SPEED_100;
> > - else
> > - state->speed = SPEED_10;
> > -
> > - state->pause = 0;
> > - fcc_reg = axienet_ior(lp, XAE_FCC_OFFSET);
> > - if (fcc_reg & XAE_FCC_FCTX_MASK)
> > - state->pause |= MLO_PAUSE_TX;
> > - if (fcc_reg & XAE_FCC_FCRX_MASK)
> > - state->pause |= MLO_PAUSE_RX;
> > -
> > - state->an_complete = 0;
> > - state->duplex = 1;
> > + switch (state->interface) {
> > + case PHY_INTERFACE_MODE_SGMII:
> > + case PHY_INTERFACE_MODE_1000BASEX:
> > + phylink_mii_c22_pcs_get_state(lp->pcs_phy, state);
> > + break;
> > + default:
> > + break;
> > + }
> > }
> >
> > static void axienet_mac_an_restart(struct phylink_config *config)
> > {
> > - /* Unsupported, do nothing */
> > + struct net_device *ndev = to_net_dev(config->dev);
> > + struct axienet_local *lp = netdev_priv(ndev);
> > +
> > + phylink_mii_c22_pcs_an_restart(lp->pcs_phy);
>
> Is this phylink.._an_restart only called for 1000BaseX/SGMII?
Yes, this is only called in phylink_mac_pcs_an_restart and only if
phy_interface_mode_is_8023z returns true (only for 1000BaseX or
2500BaseX).
> > }
> >
> > static void axienet_mac_config(struct phylink_config *config,
> > unsigned int
> > mode,
> > const struct phylink_link_state *state)
> > {
> > - /* nothing meaningful to do */
> > + struct net_device *ndev = to_net_dev(config->dev);
> > + struct axienet_local *lp = netdev_priv(ndev);
> > + int ret;
> > +
> > + switch (state->interface) {
> > + case PHY_INTERFACE_MODE_SGMII:
> > + case PHY_INTERFACE_MODE_1000BASEX:
> > + ret = phylink_mii_c22_pcs_config(lp->pcs_phy, mode,
> > + state->interface,
> > + state->advertising);
> > + if (ret < 0)
> > + netdev_warn(ndev, "Failed to configure PCS:
> > %d\n",
> > + ret);
> > + break;
> > +
> > + default:
> > + break;
> > + }
> > }
> >
> > static void axienet_mac_link_down(struct phylink_config *config,
> > @@ -1999,6 +2026,20 @@ static int axienet_probe(struct
> > platform_device
> > *pdev)
> > dev_warn(&pdev->dev,
> > "error registering MDIO bus: %d\n",
> > ret);
> > }
>
> Minor nit - There is already a check for phy_node at L1882. Maybe we
> can refactor and use it.
Possible, but then we need to duplicate the check for 1000BaseX/SGMII
again before looking for pcs_phy - doesn't seem like a clear win.
> if (!lp->phy_node) {
> if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII || BASEX)
> //error handing
> } else {
> //existing code
> }
>
> > + if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||
> > + lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
> > + if (!lp->phy_node) {
> > + dev_err(&pdev->dev, "phy-handle required for
> > 1000BaseX/SGMII\n");
> > + ret = -EINVAL;
> > + goto free_netdev;
> > + }
> > + lp->pcs_phy = of_mdio_find_device(lp->phy_node);
> > + if (!lp->pcs_phy) {
> > + ret = -EPROBE_DEFER;
>
> Are we assuming the error is always EPROBE_DEFER?
As Russell mentioned, I believe the device not being found is the only
error possible here.
> > + goto free_netdev;
> > + }
> > + lp->phylink_config.pcs_poll = true;
> > + }
> >
> > lp->phylink_config.dev = &ndev->dev;
> > lp->phylink_config.type = PHYLINK_NETDEV;
> > @@ -2036,6 +2077,9 @@ static int axienet_remove(struct
> > platform_device
> > *pdev)
> > if (lp->phylink)
> > phylink_destroy(lp->phylink);
> >
> > + if (lp->pcs_phy)
> > + put_device(&lp->pcs_phy->dev);
> > +
> > axienet_mdio_teardown(lp);
> >
> > clk_disable_unprepare(lp->clk);
> > --
> > 2.18.4
Powered by blists - more mailing lists