lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 27 Oct 2020 23:27:42 +0000 From: "Badel, Laurent" <LaurentBadel@...on.com> To: "davem@...emloft.net" <davem@...emloft.net>, "m.felsch@...gutronix.de" <m.felsch@...gutronix.de>, "fugang.duan@....com" <fugang.duan@....com>, "kuba@...nel.org" <kuba@...nel.org>, "andrew@...n.ch" <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>, "linux@...linux.org.uk" <linux@...linux.org.uk>, "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>, "lgirdwood@...il.com" <lgirdwood@...il.com>, "broonie@...nel.org" <broonie@...nel.org>, "robh+dt@...nel.org" <robh+dt@...nel.org>, "richard.leitner@...data.com" <richard.leitner@...data.com>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, "f.fainelli@...il.com" <f.fainelli@...il.com> CC: "Quette, Arnaud" <ArnaudQuette@...on.com> Subject: [PATCH net 2/4] net:phy:smsc: expand documentation of clocks property Subject: [PATCH net 2/4] net:phy:smsc: expand documentation of clocks property Description: The ref clock is managed differently when added to the DT entry for SMSC PHY. Thus, specify this more clearly in the documentation. Signed-off-by: Laurent Badel <laurentbadel@...on.com> --- Documentation/devicetree/bindings/net/smsc-lan87xx.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/smsc-lan87xx.txt b/Documentation/devicetree/bindings/net/smsc-lan87xx.txt index a8d0dc9a8c0e..43f4763f0d3d 100644 --- a/Documentation/devicetree/bindings/net/smsc-lan87xx.txt +++ b/Documentation/devicetree/bindings/net/smsc-lan87xx.txt @@ -7,7 +7,8 @@ Optional properties: - clocks: The clock used as phy reference clock and is connected to phy - pin XTAL1/CLKIN. + pin XTAL1/CLKIN. If set, the clock will be managed by the PHY + driver and remain enabled for the lifetime of the driver. - smsc,disable-energy-detect: If set, do not enable energy detect mode for the SMSC phy. -- 2.17.1 ----------------------------- Eaton Industries Manufacturing GmbH ~ Registered place of business: Route de la Longeraie 7, 1110, Morges, Switzerland -----------------------------
Powered by blists - more mailing lists