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Message-ID: <20201102023809.GA10673@yilunxu-OptiPlex-7050>
Date: Mon, 2 Nov 2020 10:38:09 +0800
From: Xu Yilun <yilun.xu@...el.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: jesse.brandeburg@...el.com, anthony.l.nguyen@...el.com,
davem@...emloft.net, kuba@...nel.org, mdf@...nel.org,
lee.jones@...aro.org, linux-kernel@...r.kernel.org,
linux-fpga@...r.kernel.org, netdev@...r.kernel.org,
trix@...hat.com, lgoncalv@...hat.com, hao.wu@...el.com,
yilun.xu@...el.com
Subject: Re: [RFC PATCH 1/6] docs: networking: add the document for DFL Ether
Group driver
Hi Andrew:
On Mon, Oct 26, 2020 at 08:14:00PM +0100, Andrew Lunn wrote:
> > > > > Do you really mean PHY? I actually expect it is PCS?
> > > >
> > > > For this implementation, yes.
> > >
> > > Yes, you have a PHY? Or Yes, it is PCS?
> >
> > Sorry, I mean I have a PHY.
> >
> > >
> > > To me, the phylib maintainer, having a PHY means you have a base-T
> > > interface, 25Gbase-T, 40Gbase-T? That would be an odd and expensive
> > > architecture when you should be able to just connect SERDES interfaces
> > > together.
>
> You really have 25Gbase-T, 40Gbase-T? Between the FPGA & XL710?
> What copper PHYs are using?
>
> > I see your concerns about the SERDES interface between FPGA & XL710.
>
> I have no concerns about direct SERDES connections. That is the normal
> way of doing this. It keeps it a lot simpler, since you don't have to
> worry about driving the PHYs.
>
I did some investigation and now I have some details.
The term 'PHY' described in Ether Group Spec should be the PCS + PMA, a figure
below for one configuration:
+------------------------+ +-----------------+
| Host Side Ether Group | | XL710 |
| | | |
| +--------------------+ | | |
| | 40G Ether IP | | | |
| | | | | |
| | +---------+ | | XLAUI | |
| | MAC - |PCS - PMA| | |----------| PMA - PCS - MAC |
| | +---------+ | | | |
+-+--------------------+-+ +-----------------+
Thanks,
Yilun
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