netdev - Re: Fwd: net: fec: rx descriptor ring out of order

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Date:   Fri, 13 Nov 2020 13:21:16 +0100
From:   Kegl Rohit <keglrohit@...il.com>
To:     David Laight <David.Laight@...lab.com>,
        Andy Duan <fugang.duan@....com>
Cc:     Eric Dumazet <eric.dumazet@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: Re: Fwd: net: fec: rx descriptor ring out of order

On Fri, Nov 13, 2020 at 8:33 AM Kegl Rohit <keglrohit@...il.com> wrote:
>
> > What are the addresses of the ring entries?
> > I bet there is something wrong with the cache coherency and/or
> > flushing.
> >
> > So the MAC hardware has done the write but (somewhere) it
> > isn't visible to the cpu for ages.
>
> CMA memory is disabled in our kernel config.
> So the descriptors allocated with dma_alloc_coherent() won't be CMA memory.
> Could this cause a different caching/flushing behaviour?

Yes, after tests I think it is caused by the disabled CMA.

@Andy
I could find this mail and the attached "i.MX6 dma memory bufferable
issue.pptx" in the archive
https://marc.info/?l=linux-netdev&m=140135147823760
Was this issue solved in some kernel versions later on?
Is CMA still necessary with a 5.4 Kernel?