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Message-ID: <20201117015325.GB26272@hoboy.vegasvil.org>
Date: Mon, 16 Nov 2020 17:53:25 -0800
From: Richard Cochran <richardcochran@...il.com>
To: Jakub Kicinski <kuba@...nel.org>
Cc: Tony Nguyen <anthony.l.nguyen@...el.com>, davem@...emloft.net,
Piotr Kwapulinski <piotr.kwapulinski@...el.com>,
netdev@...r.kernel.org, sassmann@...hat.com,
Aleksandr Loktionov <aleksandr.loktionov@...el.com>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
Andrew Bowers <andrewx.bowers@...el.com>,
Vladimir Oltean <olteanv@...il.com>
Subject: Re: [net-next 1/4] i40e: add support for PTP external
synchronization clock
On Mon, Nov 16, 2020 at 05:07:37PM -0800, Jakub Kicinski wrote:
> On Fri, 13 Nov 2020 16:10:54 -0800 Tony Nguyen wrote:
> > +/* get PTP pins for ioctl */
> > +#define SIOCGPINS (SIOCDEVPRIVATE + 0)
> > +/* set PTP pins for ioctl */
> > +#define SIOCSPINS (SIOCDEVPRIVATE + 1)
>
> This is unexpected.. is it really normal to declare private device
> IOCTLs to configure PPS pins? Or are you just exposing this so you're
> able to play with GPIOs from user space?
I missed the full patch, but I'd like to point out that we already
have a rather fully featured pin control API. If something is missing
from that API, then please, let's discuss it!
Thanks,
Richard
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