netdev - Re: [PATCH net 1/2] ibmvnic: Ensure that SCRQ entry reads are correctly ordered

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 25 Nov 2020 09:26:01 -0600
From:   Thomas Falcon <tlfalcon@...ux.ibm.com>
To:     Michael Ellerman <mpe@...erman.id.au>, netdev@...r.kernel.org
Cc:     cforno12@...ux.ibm.com, ljp@...ux.vnet.ibm.com,
        ricklind@...ux.ibm.com, dnbanerg@...ibm.com,
        drt@...ux.vnet.ibm.com, brking@...ux.vnet.ibm.com,
        sukadev@...ux.vnet.ibm.com, linuxppc-dev@...ts.ozlabs.org
Subject: Re: [PATCH net 1/2] ibmvnic: Ensure that SCRQ entry reads are
 correctly ordered

On 11/24/20 11:43 PM, Michael Ellerman wrote:
> Thomas Falcon <tlfalcon@...ux.ibm.com> writes:
>> Ensure that received Subordinate Command-Response Queue (SCRQ)
>> entries are properly read in order by the driver. These queues
>> are used in the ibmvnic device to process RX buffer and TX completion
>> descriptors. dma_rmb barriers have been added after checking for a
>> pending descriptor to ensure the correct descriptor entry is checked
>> and after reading the SCRQ descriptor to ensure the entire
>> descriptor is read before processing.
>>
>> Fixes: 032c5e828 ("Driver for IBM System i/p VNIC protocol")
>> Signed-off-by: Thomas Falcon <tlfalcon@...ux.ibm.com>
>> ---
>>   drivers/net/ethernet/ibm/ibmvnic.c | 8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
>> index 2aa40b2..489ed5e 100644
>> --- a/drivers/net/ethernet/ibm/ibmvnic.c
>> +++ b/drivers/net/ethernet/ibm/ibmvnic.c
>> @@ -2403,6 +2403,8 @@ static int ibmvnic_poll(struct napi_struct *napi, int budget)
>>   
>>   		if (!pending_scrq(adapter, adapter->rx_scrq[scrq_num]))
>>   			break;
>> +		/* ensure that we do not prematurely exit the polling loop */
>> +		dma_rmb();
> I'd be happier if these comments were more specific about which read(s)
> they are ordering vs which other read(s).
>
> I'm sure it's obvious to you, but it may not be to a future author,
> and/or after the code has been refactored over time.

Thank you for reviewing! I will submit a v2 soon with clearer comments 
on the reads being ordered here.

Thanks,

Tom


>
>>   		next = ibmvnic_next_scrq(adapter, adapter->rx_scrq[scrq_num]);
>>   		rx_buff =
>>   		    (struct ibmvnic_rx_buff *)be64_to_cpu(next->
>> @@ -3098,6 +3100,9 @@ static int ibmvnic_complete_tx(struct ibmvnic_adapter *adapter,
>>   		unsigned int pool = scrq->pool_index;
>>   		int num_entries = 0;
>>   
>> +		/* ensure that the correct descriptor entry is read */
>> +		dma_rmb();
>> +
>>   		next = ibmvnic_next_scrq(adapter, scrq);
>>   		for (i = 0; i < next->tx_comp.num_comps; i++) {
>>   			if (next->tx_comp.rcs[i]) {
>> @@ -3498,6 +3503,9 @@ static union sub_crq *ibmvnic_next_scrq(struct ibmvnic_adapter *adapter,
>>   	}
>>   	spin_unlock_irqrestore(&scrq->lock, flags);
>>   
>> +	/* ensure that the entire SCRQ descriptor is read */
>> +	dma_rmb();
>> +
>>   	return entry;
>>   }
> cheers