lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Fri, 11 Dec 2020 11:13:31 +0100 From: Thomas Gleixner <tglx@...utronix.de> To: Jürgen Groß <jgross@...e.com>, boris.ostrovsky@...cle.com, LKML <linux-kernel@...r.kernel.org> Cc: Peter Zijlstra <peterz@...radead.org>, Marc Zyngier <maz@...nel.org>, Stefano Stabellini <sstabellini@...nel.org>, xen-devel@...ts.xenproject.org, "James E.J. Bottomley" <James.Bottomley@...senPartnership.com>, Helge Deller <deller@....de>, afzal mohammed <afzal.mohd.ma@...il.com>, linux-parisc@...r.kernel.org, Russell King <linux@...linux.org.uk>, linux-arm-kernel@...ts.infradead.org, Mark Rutland <mark.rutland@....com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, Christian Borntraeger <borntraeger@...ibm.com>, Heiko Carstens <hca@...ux.ibm.com>, linux-s390@...r.kernel.org, Jani Nikula <jani.nikula@...ux.intel.com>, Joonas Lahtinen <joonas.lahtinen@...ux.intel.com>, Rodrigo Vivi <rodrigo.vivi@...el.com>, David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>, Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@...el.com>, Chris Wilson <chris@...is-wilson.co.uk>, Wambui Karuga <wambui.karugax@...il.com>, intel-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org, Tvrtko Ursulin <tvrtko.ursulin@...ux.intel.com>, Linus Walleij <linus.walleij@...aro.org>, linux-gpio@...r.kernel.org, Lee Jones <lee.jones@...aro.org>, Jon Mason <jdmason@...zu.us>, Dave Jiang <dave.jiang@...el.com>, Allen Hubbe <allenbh@...il.com>, linux-ntb@...glegroups.com, Lorenzo Pieralisi <lorenzo.pieralisi@....com>, Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, Michal Simek <michal.simek@...inx.com>, linux-pci@...r.kernel.org, Karthikeyan Mitran <m.karthikeyan@...iveil.co.in>, Hou Zhiqiang <Zhiqiang.Hou@....com>, Tariq Toukan <tariqt@...dia.com>, "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org, linux-rdma@...r.kernel.org, Saeed Mahameed <saeedm@...dia.com>, Leon Romanovsky <leon@...nel.org> Subject: Re: [patch 27/30] xen/events: Only force affinity mask for percpu interrupts On Fri, Dec 11 2020 at 07:17, Jürgen Groß wrote: > On 11.12.20 00:20, boris.ostrovsky@...cle.com wrote: >> >> On 12/10/20 2:26 PM, Thomas Gleixner wrote: >>> All event channel setups bind the interrupt on CPU0 or the target CPU for >>> percpu interrupts and overwrite the affinity mask with the corresponding >>> cpumask. That does not make sense. >>> >>> The XEN implementation of irqchip::irq_set_affinity() already picks a >>> single target CPU out of the affinity mask and the actual target is stored >>> in the effective CPU mask, so destroying the user chosen affinity mask >>> which might contain more than one CPU is wrong. >>> >>> Change the implementation so that the channel is bound to CPU0 at the XEN >>> level and leave the affinity mask alone. At startup of the interrupt >>> affinity will be assigned out of the affinity mask and the XEN binding will >>> be updated. >> >> >> If that's the case then I wonder whether we need this call at all and instead bind at startup time. > > This binding to cpu0 was introduced with commit 97253eeeb792d61ed2 > and I have no reason to believe the underlying problem has been > eliminated. "The kernel-side VCPU binding was not being correctly set for newly allocated or bound interdomain events. In ARM guests where 2-level events were used, this would result in no interdomain events being handled because the kernel-side VCPU masks would all be clear. x86 guests would work because the irq affinity was set during irq setup and this would set the correct kernel-side VCPU binding." I'm not convinced that this is really correctly analyzed because affinity setting is done at irq startup. switch (__irq_startup_managed(desc, aff, force)) { case IRQ_STARTUP_NORMAL: ret = __irq_startup(desc); irq_setup_affinity(desc); break; which is completely architecture agnostic. So why should this magically work on x86 and not on ARM if both are using the same XEN irqchip with the same irqchip callbacks. Thanks, tglx
Powered by blists - more mailing lists