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Date: Wed, 23 Dec 2020 02:50:07 +0000 From: patchwork-bot+netdevbpf@...nel.org To: Martin Blumenstingl <martin.blumenstingl@...glemail.com> Cc: netdev@...r.kernel.org, linux-amlogic@...ts.infradead.org, davem@...emloft.net, kuba@...nel.org, khilman@...libre.com, jbrunet@...libre.com, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, thomas.graichen@...il.com Subject: Re: [PATCH] net: stmmac: dwmac-meson8b: ignore the second clock input Hello: This patch was applied to netdev/net.git (refs/heads/master): On Sat, 19 Dec 2020 14:50:36 +0100 you wrote: > The dwmac glue registers on Amlogic Meson8b and newer SoCs has two clock > inputs: > - Meson8b and Meson8m2: MPLL2 and MPLL2 (the same parent is wired to > both inputs) > - GXBB, GXL, GXM, AXG, G12A, G12B, SM1: FCLK_DIV2 and MPLL2 > > All known vendor kernels and u-boots are using the first input only. We > let the common clock framework automatically choose the "right" parent. > For some boards this causes a problem though, specificially with G12A and > newer SoCs. The clock input is used for generating the 125MHz RGMII TX > clock. For the two input clocks this means on G12A: > - FCLK_DIV2: 999999985Hz / 8 = 124999998.125Hz > - MPLL2: 499999993Hz / 4 = 124999998.25Hz > > [...] Here is the summary with links: - net: stmmac: dwmac-meson8b: ignore the second clock input https://git.kernel.org/netdev/net/c/f87777a3c30c You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
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