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Date:   Mon, 4 Jan 2021 11:58:10 -0800
From:   Florian Fainelli <>
To:     Martin Blumenstingl <>,,
Subject: Re: [PATCH 2/2] net: dsa: lantiq_gswip: Fix GSWIP_MII_CFG(p) register

On 1/2/21 5:25 PM, Martin Blumenstingl wrote:
> There is one GSWIP_MII_CFG register for each switch-port except the CPU
> port. The register offset for the first port is 0x0, 0x02 for the
> second, 0x04 for the third and so on.
> Update the driver to not only restrict the GSWIP_MII_CFG registers to
> ports 0, 1 and 5. Handle ports 0..5 instead but skip the CPU port. This
> means we are not overwriting the configuration for the third port (port
> two since we start counting from zero) with the settings for the sixth
> port (with number five) anymore.
> The GSWIP_MII_PCDU(p) registers are not updated because there's really
> only three (one for each of the following ports: 0, 1, 5).
> Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> Cc:
> Signed-off-by: Martin Blumenstingl <>

Reviewed-by: Florian Fainelli <>

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