netdev - Re: Registering IRQ for MT7530 internal PHYs

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Message-ID: <CALW65ja33=+7TGQMYdr=Wztwy_simszSwO6saMvvSeqX3qWGxA@mail.gmail.com>
Date:   Wed, 6 Jan 2021 16:54:36 +0800
From:   DENG Qingfang <dqfext@...il.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Marc Zyngier <maz@...nel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Landen Chao <Landen.Chao@...iatek.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Russell King <linux@...linux.org.uk>,
        Sean Wang <sean.wang@...iatek.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        linux-kernel@...r.kernel.org, netdev <netdev@...r.kernel.org>,
        Weijie Gao <weijie.gao@...iatek.com>,
        Chuanhong Guo <gch981213@...il.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        René van Dorst <opensource@...rst.com>
Subject: Re: Registering IRQ for MT7530 internal PHYs

Hi Andrew,

On Wed, Dec 30, 2020 at 11:23 PM Andrew Lunn <andrew@...n.ch> wrote:
>
> On Wed, Dec 30, 2020 at 09:42:09AM +0000, Marc Zyngier wrote:
> > > +static irqreturn_t
> > > +mt7530_irq(int irq, void *data)
> > > +{
> > > +   struct mt7530_priv *priv = data;
> > > +   bool handled = false;
> > > +   int phy;
> > > +   u32 val;
> > > +
> > > +   val = mt7530_read(priv, MT7530_SYS_INT_STS);
> > > +   mt7530_write(priv, MT7530_SYS_INT_STS, val);
> >
> > If that is an ack operation, it should be dealt with as such in
> > an irqchip callback instead of being open-coded here.
>
> Hi Qingfang
>
> Does the PHY itself have interrupt control and status registers?

MT7531's internal PHY has an interrupt status register, but I don't
know if the same applies to MT7530.

>
> My experience with the Marvell Switch and its embedded PHYs is that
> the PHYs are just the same as the discrete PHYs. There are bits to
> enable different interrupts, and there are status bits indicating what
> event caused the interrupt. Clearing the interrupt in the PHY clears
> the interrupt in the switch interrupt controller. So in the mv88e6xxx
> interrupt code, you see i do a read of the switch interrupt controller
> status register, but i don't write to it as you have done.
>
>        Andrew