netdev - Re: [RESEND PATCH 2/2] misc: add support for retimers interfaces on Intel MAX 10 BMC

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Message-ID: <20210108020829.GC13860@yilunxu-OptiPlex-7050>
Date:   Fri, 8 Jan 2021 10:08:29 +0800
From:   Xu Yilun <yilun.xu@...el.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Greg KH <gregkh@...uxfoundation.org>, arnd@...db.de,
        lee.jones@...aro.org, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, trix@...hat.com, lgoncalv@...hat.com,
        hao.wu@...el.com, matthew.gerlach@...el.com,
        russell.h.weight@...el.com, yilun.xu@...el.com
Subject: Re: [RESEND PATCH 2/2] misc: add support for retimers interfaces on
  Intel MAX 10 BMC

On Thu, Jan 07, 2021 at 03:51:38PM +0100, Andrew Lunn wrote:
> On Thu, Jan 07, 2021 at 10:26:12AM +0100, Greg KH wrote:
> > On Thu, Jan 07, 2021 at 02:07:08PM +0800, Xu Yilun wrote:
> > > This driver supports the ethernet retimers (C827) for the Intel PAC
> > > (Programmable Acceleration Card) N3000, which is a FPGA based Smart NIC.
> > > 
> > > C827 is an Intel(R) Ethernet serdes transceiver chip that supports
> > > up to 100G transfer. On Intel PAC N3000 there are 2 C827 chips
> > > managed by the Intel MAX 10 BMC firmware. They are configured in 4 ports
> > > 10G/25G retimer mode. Host could query their link states and firmware
> > > version information via retimer interfaces (Shared registers) on Intel
> > > MAX 10 BMC. The driver creates sysfs interfaces for users to query these
> > > information.
> > 
> > Networking people, please look at this sysfs file:
> > 
> > > +What:		/sys/bus/platform/devices/n3000bmc-retimer.*.auto/link_statusX
> > > +Date:		Jan 2021
> > > +KernelVersion:	5.12
> > > +Contact:	Xu Yilun <yilun.xu@...el.com>
> > > +Description:	Read only. Returns the status of each line side link. "1" for
> > > +		link up, "0" for link down.
> > > +		Format: "%u".
> > 
> > as I need your approval to add it because it is not the "normal" way for
> > link status to be exported to userspace.
> 
> Hi Greg
> 
> Correct, this is not going to be acceptable.
> 
> The whole architecture needs to cleanly fit into the phylink model for
> controlling the SFP and the retimer.
> 
> I'm guessing Intel needs to rewrite portions of the BMC firmware to
> either transparently pass through access to the SFP socket and the
> retimer for phylink and a C827 specific driver, or add a high level
> API which a MAC driver can use, and completely hide away these PHY
> details from Linux, which is what many of the Intel Ethernet drivers
> do.

Got it, Thanks for your explanation.

Yilun