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Message-ID: <CALW65jbJ2DFqLw-i91y7oRfRhcukHSAS3A0XMuy4kA+1AtLtLQ@mail.gmail.com>
Date: Tue, 19 Jan 2021 11:20:48 +0800
From: DENG Qingfang <dqfext@...il.com>
To: Linus Walleij <linus.walleij@...aro.org>
Cc: Andrew Lunn <andrew@...n.ch>,
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Landen Chao <Landen.Chao@...iatek.com>,
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"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
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René van Dorst <opensource@...rst.com>,
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Subject: Re: [PATCH net-next 2/2] drivers: net: dsa: mt7530: MT7530 optional
GPIO support
Hi Linus,
On Mon, Jan 18, 2021 at 10:55 PM Linus Walleij <linus.walleij@...aro.org> wrote:
>
> So for offset 0..14 this becomes bits
> 0, 1, 2, 4, 5, 6, 8, 9, 10, 12 ... 18
>
> What is the logic in this and is it what you intend?
Yes. Bit 0..2 are phy 0's LED 0..2, bit 4..6 are phy 1's LED 0..2, etc.
> Please add a comment explaining what the offset is supposed
> to become for offsets 0..14 and why.
I already added to mt7530.h, perhaps I should copy it here?
>
> > + gc->ngpio = 15;
>
> And it really IS 15 not 16? Not that I know network equipment
> very well...
Yes, 3 LEDs for each phy.
>
> Yours,
> Linus Walleij
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