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Message-ID: <20210122001157.GE4147@nvidia.com>
Date: Thu, 21 Jan 2021 20:11:57 -0400
From: Jason Gunthorpe <jgg@...dia.com>
To: "Samudrala, Sridhar" <sridhar.samudrala@...el.com>
CC: Saeed Mahameed <saeed@...nel.org>,
"David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>, <netdev@...r.kernel.org>,
<linux-rdma@...r.kernel.org>, <alexander.duyck@...il.com>,
<edwin.peer@...adcom.com>, <dsahern@...nel.org>,
<kiran.patil@...el.com>, <jacob.e.keller@...el.com>,
<david.m.ertman@...el.com>, <dan.j.williams@...el.com>,
Parav Pandit <parav@...dia.com>,
Saeed Mahameed <saeedm@...dia.com>
Subject: Re: [net-next V9 14/14] net/mlx5: Add devlink subfunction port
documentation
On Thu, Jan 21, 2021 at 12:59:55PM -0800, Samudrala, Sridhar wrote:
> > + mlx5_core.sf.4
> > + (subfunction auxiliary device)
> > + /\
> > + / \
> > + / \
> > + / \
> > + / \
> > + mlx5_core.eth.4 mlx5_core.rdma.4
> > + (sf eth aux dev) (sf rdma aux dev)
> > + | |
> > + | |
> > + p0sf88 mlx5_0
> > + (sf netdev) (sf rdma device)
>
> This picture seems to indicate that when SF is activated, a sub
> function auxiliary device is created
Yes
> and when a driver is bound to that sub function aux device and
> probed, 2 additional auxiliary devices are created.
More than two, but yes
> Is this correct? Are all these auxiliary devices seen on the same
> aux bus?
Yes
> Why do we need another sf eth aux device?
The first aux device represents the physical HW and mlx5_core binds to it,
the analog is like a pci_device.
The other aux devices represent the subsystem split of the mlx5 driver
- mlx5_core creates them and each subsystem in turn binds to the
mlx5_core driver. This already exists, and Intel will be doing this as
well whenever the RDMA driver is posted again..
Jason
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