netdev - Re: [PATCH] dsa: vsc73xx: add support for vlan filtering

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Message-ID: <20210124234509.c4wkoauiqchv4aan@skbuf>
Date:   Mon, 25 Jan 2021 01:45:09 +0200
From:   Vladimir Oltean <olteanv@...il.com>
To:     Linus Walleij <linus.walleij@...aro.org>
Cc:     Pawel Dembicki <paweldembicki@...il.com>,
        netdev <netdev@...r.kernel.org>, Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] dsa: vsc73xx: add support for vlan filtering

On Mon, Jan 25, 2021 at 12:19:55AM +0100, Linus Walleij wrote:
> This is due to the internal architecture of the switch, while it does
> have an internal tagging format, this is stripped off before letting
> it exit through the CPU port, and tagged on by the hardware
> whenever the CPU transmits something. So these tags are
> invisible to the CPU.
>
> Itr would be neat if there was some bit in the switch we could
> flick and then  the internal tagging format would come out on
> the CPU port, but sadly this does not exist.
>
> The vendors idea is that the switch should be programmed
> internally as it contains an 8051 processor that can indeed see
> the internal tags. This makes a lot of sense when the chips are
> used for a hardware switch, i.e. a box with several ethernet ports
> on it. Sadly it is not very well adopted for the usecase of smart
> operating system like linux hogging into the CPU port and
> using it as a managed switch. :/
>
> We currently have the 8051 processor in the switch disabled.

The sad part of me not having access to any Sparx-G5e documentation
other than product briefs is that I can't actually be fully convinced
that this is true without seeing it. Other Vitesse switches support
DSA tagging towards an external CPU, so if these ones don't, the
Node Processor Interface feature must have been added later.

Anyhow, you did not approve or disprove the tag_8021q idea.
With VLAN trunking on the CPU port, how would per-port traffic be
managed? Would it be compatible with hardware-accelerated bridging
(which this driver still does not support)?