lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CO6PR18MB38739ED82AB44815ADAC3DBAB0BE9@CO6PR18MB3873.namprd18.prod.outlook.com>
Date:   Sun, 24 Jan 2021 13:24:01 +0000
From:   Stefan Chulski <stefanc@...vell.com>
To:     Russell King - ARM Linux admin <linux@...linux.org.uk>
CC:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "thomas.petazzoni@...tlin.com" <thomas.petazzoni@...tlin.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        Nadav Haklai <nadavh@...vell.com>,
        Yan Markman <ymarkman@...vell.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "mw@...ihalf.com" <mw@...ihalf.com>,
        "andrew@...n.ch" <andrew@...n.ch>,
        "atenart@...nel.org" <atenart@...nel.org>
Subject: RE: [EXT] Re: [PATCH v2 RFC net-next 09/18] net: mvpp2: add FCA RXQ
 non occupied descriptor threshold

> > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
> > @@ -1154,6 +1154,9 @@ static void mvpp2_interrupts_mask(void *arg)
> >  	mvpp2_thread_write(port->priv,
> >  			   mvpp2_cpu_to_thread(port->priv,
> smp_processor_id()),
> >  			   MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
> > +	mvpp2_thread_write(port->priv,
> > +			   mvpp2_cpu_to_thread(port->priv,
> smp_processor_id()),
> > +			   MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
> 
> I wonder if this should be refactored:
> 
> 	u32 thread = mvpp2_cpu_to_thread(port->priv,
> smp_processor_id());
> 
> 	mvpp2_thread_write(port->priv, thread,
> 			   MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
> 	mvpp2_thread_write(port->priv, thread,
> 			   MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
> 
> to avoid having to recompute mvpp2_cpu_to_thread() for each write?
> 
> However, looking deeper...
> 
> static void mvpp2_interrupts_mask(void *arg) {
> 	struct mvpp2_port *port = arg;
> 	u32 thread;
> 	int cpu;
> 
> 	cpu = smp_processor_id();
> 	if (cpu > port->priv->nthreads)
> 		return
> 
> 	thread = mvpp2_cpu_to_thread(port->priv, cpu);
> 	...
> 
> and I wonder about that condition - "cpu > port->priv->nthreads". If cpu ==
> port->priv->nthreads, then mvpp2_cpu_to_thread() will return zero, just like
> the cpu=0 case. This leads me to suspect that this comparison off by one.

I can push patch that make it if (cpu => port->priv->nthreads). Or even remove this if.
Anyway on current Armada platforms we have only 4 CPU's and maximum 9 PPv2 threads(nthreads is min between  num_present_cpus and maximum HW PPv2 threads), so this would be always false.

Regards,
Stefan. 


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ