netdev - Re: [pull request][net-next V10 00/14] Add mlx5 subfunction support

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Message-ID: <20210125195905.GA4147@nvidia.com>
Date:   Mon, 25 Jan 2021 15:59:05 -0400
From:   Jason Gunthorpe <jgg@...dia.com>
To:     Edwin Peer <edwin.peer@...adcom.com>
CC:     Parav Pandit <parav@...dia.com>, Saeed Mahameed <saeed@...nel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        netdev <netdev@...r.kernel.org>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        Alexander Duyck <alexander.duyck@...il.com>,
        Sridhar Samudrala <sridhar.samudrala@...el.com>,
        David Ahern <dsahern@...nel.org>,
        Kiran Patil <kiran.patil@...el.com>,
        Jacob Keller <jacob.e.keller@...el.com>,
        "Ertman, David M" <david.m.ertman@...el.com>,
        Dan Williams <dan.j.williams@...el.com>,
        Saeed Mahameed <saeedm@...dia.com>
Subject: Re: [pull request][net-next V10 00/14] Add mlx5 subfunction support

On Mon, Jan 25, 2021 at 11:34:49AM -0800, Edwin Peer wrote:

> What do these amount to in practice? Presumably config space is backed
> by normal memory controlled by firmware. Do VF's need to expose ECAM?
> Also, don't MSI tables come out of the BAR budget? Is the required BAR
> space necessarily more than any other addressable unit that can be
> delegated to a SF?

Every writable data mandated by the PCI spec requires very expensive
on-die SRAM to store it.

We've seen Intel drivers that show their SIOV ADIs don't even have a
register file and the only PCI presence is just a write-only doorbell
page in the BAR.

It is hard to argue a write-only register in a BAR page vs all the
SRIOV trappings when it comes to HW cost.

Jason