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Message-ID: <DB8PR04MB6795C4AFFBC2CC1FB189F1FBE6BB0@DB8PR04MB6795.eurprd04.prod.outlook.com>
Date: Wed, 27 Jan 2021 01:44:42 +0000
From: Joakim Zhang <qiangqing.zhang@....com>
To: Willem de Bruijn <willemdebruijn.kernel@...il.com>
CC: Giuseppe Cavallaro <peppe.cavallaro@...com>,
Alexandre Torgue <alexandre.torgue@...com>,
Jose Abreu <joabreu@...opsys.com>,
David Miller <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Network Development <netdev@...r.kernel.org>,
dl-linux-imx <linux-imx@....com>, Andrew Lunn <andrew@...n.ch>,
Florian Fainelli <f.fainelli@...il.com>
Subject: RE: [PATCH V3 2/6] net: stmmac: stop each tx channel independently
> -----Original Message-----
> From: Willem de Bruijn <willemdebruijn.kernel@...il.com>
> Sent: 2021年1月27日 7:10
> To: Joakim Zhang <qiangqing.zhang@....com>
> Cc: Giuseppe Cavallaro <peppe.cavallaro@...com>; Alexandre Torgue
> <alexandre.torgue@...com>; Jose Abreu <joabreu@...opsys.com>; David
> Miller <davem@...emloft.net>; Jakub Kicinski <kuba@...nel.org>; Network
> Development <netdev@...r.kernel.org>; dl-linux-imx <linux-imx@....com>;
> Andrew Lunn <andrew@...n.ch>; Florian Fainelli <f.fainelli@...il.com>
> Subject: Re: [PATCH V3 2/6] net: stmmac: stop each tx channel independently
>
> On Tue, Jan 26, 2021 at 7:03 AM Joakim Zhang <qiangqing.zhang@....com>
> wrote:
> >
> > If clear GMAC_CONFIG_TE bit, it would stop all tx channels, but users
> > may only want to stop secific tx channel.
>
> secific -> specific
Thanks. Will correct it.
> >
> > Fixes: 48863ce5940f ("stmmac: add DMA support for GMAC 4.xx")
> > Signed-off-by: Joakim Zhang <qiangqing.zhang@....com>
> > ---
> > drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 4 ----
> > 1 file changed, 4 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
> > b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
> > index 0b4ee2dbb691..71e50751ef2d 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
> > @@ -53,10 +53,6 @@ void dwmac4_dma_stop_tx(void __iomem *ioaddr,
> u32
> > chan)
> >
> > value &= ~DMA_CONTROL_ST;
> > writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
> > -
> > - value = readl(ioaddr + GMAC_CONFIG);
> > - value &= ~GMAC_CONFIG_TE;
> > - writel(value, ioaddr + GMAC_CONFIG);
>
> Is it safe to partially unwind the actions of dwmac4_dma_start_tx
>
> And would the same reasoning apply to dwmac4_(dma_start|stop)_rx?
Sorry, I am not quite understand what you means.
What this patch did is to align to dwmac4_(dma_start|stop)_rx.
dwmac4_dma_start_rx: assert DMA_CONTROL_SR bit for each channel, and assert GMAC_CONFIG_RE bit which targets all channels.
dwmac4_dma_stop_rx: only need clear DMA_CONTROL_SR bit for each channel.
After this patch applied:
dwmac4_dma_start_tx: assert DMA_CONTROL_ST bit for each channel, and assert GMAC_CONFIG_TE bit which targets all channels.
dwmac4_dma_stop_tx: only need clear DMA_CONTROL_ST bit for each channel.
You can refer to drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c, this is the correct sequence.
Thanks.
Best Regards,
Joakim Zhang
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