netdev - RE: [PATCH 09/22] RDMA/irdma: Implement HW Admin Queue OPs

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Message-ID: <610ec40cfc71437dadc802da3e8d3b35@intel.com>
Date:   Sat, 30 Jan 2021 01:18:56 +0000
From:   "Saleem, Shiraz" <shiraz.saleem@...el.com>
To:     Jason Gunthorpe <jgg@...dia.com>
CC:     "dledford@...hat.com" <dledford@...hat.com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "Ertman, David M" <david.m.ertman@...el.com>,
        "Nguyen, Anthony L" <anthony.l.nguyen@...el.com>,
        "Ismail, Mustafa" <mustafa.ismail@...el.com>
Subject: RE: [PATCH 09/22] RDMA/irdma: Implement HW Admin Queue OPs

> Subject: Re: [PATCH 09/22] RDMA/irdma: Implement HW Admin Queue OPs
> 
> On Wed, Jan 27, 2021 at 12:41:59AM +0000, Saleem, Shiraz wrote:
> > > Subject: Re: [PATCH 09/22] RDMA/irdma: Implement HW Admin Queue OPs
> > >
> > > On Fri, Jan 22, 2021 at 05:48:14PM -0600, Shiraz Saleem wrote:
> > > > +#define LS_64_1(val, bits)	((u64)(uintptr_t)(val) << (bits))
> > > > +#define RS_64_1(val, bits)	((u64)(uintptr_t)(val) >> (bits))
> > > > +#define LS_32_1(val, bits)	((u32)((val) << (bits)))
> > > > +#define RS_32_1(val, bits)	((u32)((val) >> (bits)))
> > > > +#define LS_64(val, field)	(((u64)(val) << field ## _S) & (field ## _M))
> > > > +#define RS_64(val, field)	((u64)((val) & field ## _M) >> field ## _S)
> > > > +#define LS_32(val, field)	(((val) << field ## _S) & (field ## _M))
> > > > +#define RS_32(val, field)	(((val) & field ## _M) >> field ## _S)
> > >
> > > Yikes, why can't this use the normal GENMASK/FIELD_PREP
> > > infrastructure like the other new drivers are now doing?
> > >
> > > EFA is not a perfect example, but EFA_GET/EFA_SET are the macros I
> > > would expect to see, just without the _MASK thing.
> > >
> > > IBA_GET/SET shows how to do that pattern
> > >
> > > > +#define FLD_LS_64(dev, val, field)	\
> > > > +	(((u64)(val) << (dev)->hw_shifts[field ## _S]) &
> > > > +(dev)->hw_masks[field ##
> > > _M])
> > > > +#define FLD_RS_64(dev, val, field)	\
> > > > +	((u64)((val) & (dev)->hw_masks[field ## _M]) >>
> > > > +(dev)->hw_shifts[field ##
> > > _S])
> > > > +#define FLD_LS_32(dev, val, field)	\
> > > > +	(((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
> > > > +#define FLD_RS_32(dev, val, field)	\
> > > > +	((u64)((val) & (dev)->hw_masks[field ## _M]) >>
> > > > +(dev)->hw_shifts[field ## _S])
> > >
> > > Is it because the register access is programmable? That shouldn't be
> > > a significant problem.
> > >
> >
> > Yes. How do we solve that?
> >
> > https://lore.kernel.org/linux-rdma/20200602232903.GD65026@mellanox.com
> > /
> 
> Ooh, I'm remarkably consistent after all this time
> 
> I think the answer hasn't changed the point is to make the macros the same.
> 
> And the LS/RS stuff isn't using the indirection, so why isn't it using normal
> GENMASK stuff?
> 
It can. And we will use FIELD_PREP / GENMASK on those that don't use the indirection.
FLD_LS/RS will be left alone.