netdev - Re: [PATCH net-next 1/4] PCI/VPD: Remove Chelsio T3 quirk

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Message-ID: <2a15d286-2f3d-9ec5-0f54-925a51427689@gmail.com>
Date:   Thu, 4 Feb 2021 08:18:52 +0100
From:   Heiner Kallweit <hkallweit1@...il.com>
To:     Jakub Kicinski <kuba@...nel.org>
Cc:     Raju Rangoju <rajur@...lsio.com>,
        David Miller <davem@...emloft.net>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: Re: [PATCH net-next 1/4] PCI/VPD: Remove Chelsio T3 quirk

On 04.02.2021 03:30, Jakub Kicinski wrote:
> On Tue, 2 Feb 2021 21:35:55 +0100 Heiner Kallweit wrote:
>> cxgb3 driver doesn't use the PCI core code for VPD access, it has its own
>> implementation. Therefore we don't need a quirk for it in the core code.
>>
>> Signed-off-by: Heiner Kallweit <hkallweit1@...il.com>
> 
> Would this not affect the size of the file under sysfs?
> 
Good point. Not the size (because it's 0 = unlimited), but the exposed
data would be limited to what can be auto-detected from offset 0.
Most T3 devices have the VPD at offset 0x0c00, and I'd expect (don't have
test hw) that there's no valid VPD structure at offset 0.
Therefore no VPD data will be exposed via sysfs. But:

- VPD data starting at an offset doesn't follow PCI spec. Therefore it's
  questionable whether anybody can expect such data to be available via sysfs.

- Typical userspace tools like lspci start parsing VPD at offset 0,
  and therefore won't recognize the VPD data also as of today.
  (again: no test hw to verify this)

- There might be Chelsio-provided userspace tools that use sysfs VPD access
  and parse the data based on knowledge of the proprietary VPD layout.
  Such a usecase would be broken now, indeed. Not sure whether any such
  tool exists, maybe Raju can comment on this.



>> diff --git a/drivers/pci/vpd.c b/drivers/pci/vpd.c
>> index 7915d10f9..db86fe226 100644
>> --- a/drivers/pci/vpd.c
>> +++ b/drivers/pci/vpd.c
>> @@ -628,22 +628,17 @@ static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
>>  {
>>  	int chip = (dev->device & 0xf000) >> 12;
>>  	int func = (dev->device & 0x0f00) >>  8;
>> -	int prod = (dev->device & 0x00ff) >>  0;
>>  
>>  	/*
>> -	 * If this is a T3-based adapter, there's a 1KB VPD area at offset
>> -	 * 0xc00 which contains the preferred VPD values.  If this is a T4 or
>> -	 * later based adapter, the special VPD is at offset 0x400 for the
>> -	 * Physical Functions (the SR-IOV Virtual Functions have no VPD
>> -	 * Capabilities).  The PCI VPD Access core routines will normally
>> +	 * If this is a T4 or later based adapter, the special VPD is at offset
>> +	 * 0x400 for the Physical Functions (the SR-IOV Virtual Functions have
>> +	 * no VPD Capabilities). The PCI VPD Access core routines will normally
>>  	 * compute the size of the VPD by parsing the VPD Data Structure at
>>  	 * offset 0x000.  This will result in silent failures when attempting
>>  	 * to accesses these other VPD areas which are beyond those computed
>>  	 * limits.
>>  	 */
>> -	if (chip == 0x0 && prod >= 0x20)
>> -		pci_set_vpd_size(dev, 8192);
>> -	else if (chip >= 0x4 && func < 0x8)
>> +	if (chip >= 0x4 && func < 0x8)
>>  		pci_set_vpd_size(dev, 2048);
>>  }
>>  
>