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Message-Id: <20210213002356.2557207-3-robert.hancock@calian.com>
Date: Fri, 12 Feb 2021 18:23:55 -0600
From: Robert Hancock <robert.hancock@...ian.com>
To: davem@...emloft.net, kuba@...nel.org,
radhey.shyam.pandey@...inx.com
Cc: linux@...linux.org.uk, netdev@...r.kernel.org,
devicetree@...r.kernel.org,
Robert Hancock <robert.hancock@...ian.com>
Subject: [PATCH net-next 2/3] dt-bindings: net: xilinx_axienet: add xlnx,switch-x-sgmii attribute
Document the new xlnx,switch-x-sgmii attribute which is used to indicate
that the Ethernet core supports dynamic switching between 1000BaseX and
SGMII.
Signed-off-by: Robert Hancock <robert.hancock@...ian.com>
---
Documentation/devicetree/bindings/net/xilinx_axienet.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
index 7360617cdedb..2cd452419ed0 100644
--- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
+++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
@@ -38,6 +38,10 @@ Optional properties:
1 to enable partial TX checksum offload,
2 to enable full TX checksum offload
- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
+- xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to
+ support both 1000BaseX and SGMII modes. If set, the phy-mode
+ should be set to match the mode selected on core reset (i.e.
+ by the basex_or_sgmii core input line).
- clocks : AXI bus clock for the device. Refer to common clock bindings.
Used to calculate MDIO clock divisor. If not specified, it is
auto-detected from the CPU clock (but only on platforms where
--
2.27.0
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