netdev - Re: [PATCH net v1 1/3] net: phy: mscc: adding LCPLL reset to VSC8514

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Date:   Mon, 15 Feb 2021 09:38:20 +0000
From:   <Bjarni.Jonasson@...rochip.com>
To:     <kuba@...nel.org>
CC:     <andrew@...n.ch>, <linux-kernel@...r.kernel.org>,
        <UNGLinuxDriver@...rochip.com>, <Steen.Hegelund@...rochip.com>,
        <linux@...linux.org.uk>, <f.fainelli@...il.com>,
        <netdev@...r.kernel.org>, <vladimir.oltean@....com>,
        <davem@...emloft.net>, <hkallweit1@...il.com>,
        <atenart@...nel.org>, <ioana.ciornei@....com>
Subject: Re: [PATCH net v1 1/3] net: phy: mscc: adding LCPLL reset to VSC8514

On Fri, 2021-02-12 at 10:53 -0800, Jakub Kicinski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Fri, 12 Feb 2021 15:06:41 +0100 Bjarni Jonasson wrote:
> > At Power-On Reset, transients may cause the LCPLL to lock onto a
> > clock that is momentarily unstable. This is normally seen in QSGMII
> > setups where the higher speed 6G SerDes is being used.
> > This patch adds an initial LCPLL Reset to the PHY (first instance)
> > to avoid this issue.
> > 
> > Signed-off-by: Steen Hegelund <steen.hegelund@...rochip.com>
> > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@...rochip.com>
> > Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514
> > PHY.")
> 
> Please make sure each commit builds cleanly with W=1 C=1.
> 
> This one appears to not build at all?

Sorry about that, I will make sure.