netdev - Re: [PATCH net] net: dsa: mt7530: setup core clock even in TRGMII mode

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Message-ID: <79be95b7-0c56-f831-2f3f-5a41006d0037@gmail.com>
Date:   Wed, 10 Mar 2021 19:21:17 -0800
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>,
        Sean Wang <sean.wang@...iatek.com>,
        Landen Chao <Landen.Chao@...iatek.com>,
        Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH net] net: dsa: mt7530: setup core clock even in TRGMII
 mode



On 3/10/2021 5:21 PM, Ilya Lipnitskiy wrote:
> A recent change to MIPS ralink reset logic made it so mt7530 actually
> resets the switch on platforms such as mt7621 (where bit 2 is the reset
> line for the switch). That exposed an issue where the switch would not
> function properly in TRGMII mode after a reset.
> 
> Reconfigure core clock in TRGMII mode to fix the issue.
> 
> Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
> 
> Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>

Reviewed-by: Florian Fainelli <f.fainelli@...il.com>
-- 
Florian