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Message-ID: <9e2db2f6a8de195ec0af1b879b75fa8bdb2bdc27.camel@microchip.com>
Date:   Tue, 16 Mar 2021 09:04:38 +0100
From:   Steen Hegelund <steen.hegelund@...rochip.com>
To:     Jakub Kicinski <kuba@...nel.org>
CC:     Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>, Andrew Lunn <andrew@...n.ch>,
        "David S. Miller" <davem@...emloft.net>,
        Microchip UNG Driver List <UNGLinuxDriver@...rochip.com>,
        <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v15 0/4] Adding the Sparx5 Serdes driver

Hi Jacub,

On Mon, 2021-03-15 at 10:26 -0700, Jakub Kicinski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, 15 Mar 2021 16:04:24 +0100 Steen Hegelund wrote:
> > Hi Kishon, Vinod, Andrew, Jacub, and David,
> > 
> > I just wanted to know if you think that the Generic PHY subsystem might
> > not be the right place for this Ethernet SerDes PHY driver after all.
> > 
> > Originally I chose this subsystem for historic reasons: The
> > Microchip/Microsemi Ocelot SerDes driver was added here when it was
> > upstreamed.
> > On the other hand the Ocelot Serdes can do both PCIe and Ethernet, so
> > it might fit the signature of a generic PHY better.
> 
> Are you saying this PHY is Ethernet only?

Yes this particular PHY is Ethernet only (but the Sparx5 also has a separate PCI PHY).

> 
> > At the moment the acceptance of the Sparx5 Serdes driver is blocking us
> > from adding the Sparx5 SwitchDev driver (to net), so it is really
> > important for us to resolve which subsystem the Serdes driver belongs
> > to.
> > 
> > I am very much looking forward to your response.
> 
> FWIW even if this is merged via gen phy subsystem we can pull it into
> net-next as well to unblock your other work in this dev cycle. You just
> need to send the patches as a pull request, based on merge-base between
> the gen phy tree and net-next.


-- 
BR
Steen

-=-=-=-=-=-=-=-=-=-=-=-=-=-=
steen.hegelund@...rochip.com


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