netdev - Re: [PATCH net] amd-xgbe: Update DMA coherency values

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Date:   Thu, 25 Mar 2021 08:51:49 -0500
From:   Tom Lendacky <thomas.lendacky@....com>
To:     Shyam Sundar S K <Shyam-sundar.S-k@....com>,
        "David S . Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org
Subject: Re: [PATCH net] amd-xgbe: Update DMA coherency values

On 3/24/21 10:09 PM, Shyam Sundar S K wrote:
> Based on the IOMMU configuration, the current cache control settings can
> result in possible coherency issues. The hardware team has recommended
> new settings for the PCI device path to eliminate the issue.
> 
> Fixes: 6f595959c095 ("amd-xgbe: Adjust register settings to improve performance")
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@....com>

Acked-by: Tom Lendacky <thomas.lendacky@....com>

> ---
> 
> Please queue this patch up for stable, 4.14 and higher.
> 
>  drivers/net/ethernet/amd/xgbe/xgbe.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
> index ba8321ec1ee7..3305979a9f7c 100644
> --- a/drivers/net/ethernet/amd/xgbe/xgbe.h
> +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
> @@ -180,9 +180,9 @@
>  #define XGBE_DMA_SYS_AWCR	0x30303030
>  
>  /* DMA cache settings - PCI device */
> -#define XGBE_DMA_PCI_ARCR	0x00000003
> -#define XGBE_DMA_PCI_AWCR	0x13131313
> -#define XGBE_DMA_PCI_AWARCR	0x00000313
> +#define XGBE_DMA_PCI_ARCR	0x000f0f0f
> +#define XGBE_DMA_PCI_AWCR	0x0f0f0f0f
> +#define XGBE_DMA_PCI_AWARCR	0x00000f0f
>  
>  /* DMA channel interrupt modes */
>  #define XGBE_IRQ_MODE_EDGE	0
>