netdev - Re: [PATCH net-next v4 2/2] net: axienet: Enable more clocks

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Message-ID: <YF3QOFw7jREj03Ut@lunn.ch>
Date:   Fri, 26 Mar 2021 13:14:48 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Robert Hancock <robert.hancock@...ian.com>
Cc:     davem@...emloft.net, kuba@...nel.org,
        radhey.shyam.pandey@...inx.com, robh@...nel.org,
        devicetree@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH net-next v4 2/2] net: axienet: Enable more clocks

On Thu, Mar 25, 2021 at 06:04:38PM -0600, Robert Hancock wrote:
> This driver was only enabling the first clock on the device, regardless
> of its name. However, this controller logic can have multiple clocks
> which should all be enabled. Add support for enabling additional clocks.
> The clock names used are matching those used in the Xilinx version of this
> driver as well as the Xilinx device tree generator, except for mgt_clk
> which is not present there.
> 
> For backward compatibility, if no named clocks are present, the first
> clock present is used for determining the MDIO bus clock divider.
> 
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@...inx.com>
> Signed-off-by: Robert Hancock <robert.hancock@...ian.com>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew