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Message-ID: <20210414211322.3799afd4@carbon>
Date: Wed, 14 Apr 2021 21:13:22 +0200
From: Jesper Dangaard Brouer <brouer@...hat.com>
To: Matthew Wilcox <willy@...radead.org>
Cc: linux-kernel@...r.kernel.org, linux-mm@...ck.org,
netdev@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
linux-arm-kernel@...ts.infradead.org, linux-mips@...r.kernel.org,
Ilias Apalodimas <ilias.apalodimas@...aro.org>,
Matteo Croce <mcroce@...ux.microsoft.com>,
Grygorii Strashko <grygorii.strashko@...com>,
Arnd Bergmann <arnd@...nel.org>,
Christoph Hellwig <hch@....de>, brouer@...hat.com
Subject: Re: [PATCH 1/1] mm: Fix struct page layout on 32-bit systems
On Wed, 14 Apr 2021 12:50:52 +0100
Matthew Wilcox <willy@...radead.org> wrote:
> > That said, I think we need to have a quicker fix for the immediate
> > issue with 64-bit bit dma_addr on 32-bit arch and the misalignment hole
> > it leaves[3] in struct page. In[3] you mention ppc32, does it only
> > happens on certain 32-bit archs?
>
> AFAICT it happens on mips32, ppc32, arm32 and arc. It doesn't happen
> on x86-32 because dma_addr_t is 32-bit aligned.
(If others want to reproduce). First I could not reproduce on ARM32.
Then I found out that enabling CONFIG_XEN on ARCH=arm was needed to
cause the issue by enabling CONFIG_ARCH_DMA_ADDR_T_64BIT.
Details below signature.
--
Best regards,
Jesper Dangaard Brouer
MSc.CS, Principal Kernel Engineer at Red Hat
LinkedIn: http://www.linkedin.com/in/brouer
From file: arch/arm/Kconfig
config XEN
bool "Xen guest support on ARM"
depends on ARM && AEABI && OF
depends on CPU_V7 && !CPU_V6
depends on !GENERIC_ATOMIC64
depends on MMU
select ARCH_DMA_ADDR_T_64BIT
select ARM_PSCI
select SWIOTLB
select SWIOTLB_XEN
select PARAVIRT
help
Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
My make compile command:
export VERSION=gcc-arm-10.2-2020.11-x86_64-arm-none-linux-gnueabihf/
export CROSS_COMPILE="/home/${USER}/cross-compilers/${VERSION}/bin/arm-none-linux-gnueabihf-"
make -j8 ARCH=arm CROSS_COMPILE=$CROSS_COMPILE
Pahole output:
$ pahole -C page mm/page_alloc.o
struct page {
long unsigned int flags; /* 0 4 */
/* XXX 4 bytes hole, try to pack */
union {
struct {
struct list_head lru; /* 8 8 */
struct address_space * mapping; /* 16 4 */
long unsigned int index; /* 20 4 */
long unsigned int private; /* 24 4 */
}; /* 8 20 */
struct {
dma_addr_t dma_addr; /* 8 8 */
}; /* 8 8 */
struct {
union {
struct list_head slab_list; /* 8 8 */
struct {
struct page * next; /* 8 4 */
short int pages; /* 12 2 */
short int pobjects; /* 14 2 */
}; /* 8 8 */
}; /* 8 8 */
struct kmem_cache * slab_cache; /* 16 4 */
void * freelist; /* 20 4 */
union {
void * s_mem; /* 24 4 */
long unsigned int counters; /* 24 4 */
struct {
unsigned int inuse:16; /* 24: 0 4 */
unsigned int objects:15; /* 24:16 4 */
unsigned int frozen:1; /* 24:31 4 */
}; /* 24 4 */
}; /* 24 4 */
}; /* 8 20 */
struct {
long unsigned int compound_head; /* 8 4 */
unsigned char compound_dtor; /* 12 1 */
unsigned char compound_order; /* 13 1 */
/* XXX 2 bytes hole, try to pack */
atomic_t compound_mapcount; /* 16 4 */
unsigned int compound_nr; /* 20 4 */
}; /* 8 16 */
struct {
long unsigned int _compound_pad_1; /* 8 4 */
atomic_t hpage_pinned_refcount; /* 12 4 */
struct list_head deferred_list; /* 16 8 */
}; /* 8 16 */
struct {
long unsigned int _pt_pad_1; /* 8 4 */
pgtable_t pmd_huge_pte; /* 12 4 */
long unsigned int _pt_pad_2; /* 16 4 */
union {
struct mm_struct * pt_mm; /* 20 4 */
atomic_t pt_frag_refcount; /* 20 4 */
}; /* 20 4 */
spinlock_t ptl; /* 24 4 */
}; /* 8 20 */
struct {
struct dev_pagemap * pgmap; /* 8 4 */
void * zone_device_data; /* 12 4 */
}; /* 8 8 */
struct callback_head callback_head __attribute__((__aligned__(4))); /* 8 8 */
} __attribute__((__aligned__(8))); /* 8 24 */
union {
atomic_t _mapcount; /* 32 4 */
unsigned int page_type; /* 32 4 */
unsigned int active; /* 32 4 */
int units; /* 32 4 */
}; /* 32 4 */
atomic_t _refcount; /* 36 4 */
/* size: 40, cachelines: 1, members: 4 */
/* sum members: 36, holes: 1, sum holes: 4 */
/* forced alignments: 1, forced holes: 1, sum forced holes: 4 */
/* last cacheline: 40 bytes */
} __attribute__((__aligned__(8)));
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