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Message-ID: <c29b87f0-a6f6-10cc-624d-b9c4779675c5@gmail.com>
Date:   Mon, 24 May 2021 19:27:28 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Vladimir Oltean <olteanv@...il.com>,
        Jakub Kicinski <kuba@...nel.org>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org
Cc:     Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Vladimir Oltean <vladimir.oltean@....com>,
        Russell King <linux@...linux.org.uk>
Subject: Re: [PATCH net-next 11/13] net: dsa: sja1105: register the MDIO buses
 for 100base-T1 and 100base-TX



On 5/24/2021 4:22 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.oltean@....com>
> 
> The SJA1110 contains two types of integrated PHYs: one 100base-TX PHY
> and multiple 100base-T1 PHYs.
> 
> The access procedure for the 100base-T1 PHYs is also different than it
> is for the 100base-TX one. So we register 2 MDIO buses, one for the
> base-TX and the other for the base-T1. Each bus has an OF node which is
> a child of the "mdio" subnode of the switch, and they are recognized by
> compatible string.
> 
> Cc: Russell King <linux@...linux.org.uk>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>

Reviewed-by: Florian Fainelli <f.fainelli@...il.com>
-- 
Florian

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