netdev - Re: [PATCH net-next 05/13] net: dsa: sja1105: add a PHY interface type compatibility matrix

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20210526123715.dsfdsftwhqh6hhzk@skbuf>
Date:   Wed, 26 May 2021 15:37:15 +0300
From:   Vladimir Oltean <olteanv@...il.com>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     Jakub Kicinski <kuba@...nel.org>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org,
        Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Vladimir Oltean <vladimir.oltean@....com>
Subject: Re: [PATCH net-next 05/13] net: dsa: sja1105: add a PHY interface
 type compatibility matrix

On Mon, May 24, 2021 at 07:23:09PM -0700, Florian Fainelli wrote:
> 
> 
> On 5/24/2021 4:22 PM, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@....com>
> > 
> > On the SJA1105, all ports support the parallel "xMII" protocols (MII,
> > RMII, RGMII) except for port 4 on SJA1105R/S which supports only SGMII.
> > This was relatively easy to model, by special-casing the SGMII port.
> > 
> > On the SJA1110, certain ports can be pinmuxed between SGMII and xMII, or
> > between SGMII and an internal 100base-TX PHY. This creates problems,
> > because the driver's assumption so far was that if a port supports
> > SGMII, it uses SGMII.
> > 
> > We allow the device tree to tell us how the port pinmuxing is done, and
> > check that against a PHY interface type compatibility matrix for
> > plausibility.
> > 
> > The other big change is that instead of doing SGMII configuration based
> > on what the port supports, we do it based on what is the configured
> > phy_mode of the port.
> > 
> > The 2500base-x support added in this patch is not complete.
> > 
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
> > ---
> >  drivers/net/dsa/sja1105/sja1105.h      |  5 +++
> >  drivers/net/dsa/sja1105/sja1105_main.c | 59 +++++++++++++-------------
> >  drivers/net/dsa/sja1105/sja1105_spi.c  | 20 +++++++++
> >  3 files changed, 55 insertions(+), 29 deletions(-)
> > 
> > diff --git a/drivers/net/dsa/sja1105/sja1105.h b/drivers/net/dsa/sja1105/sja1105.h
> > index d5c0217b1f65..a27841642693 100644
> > --- a/drivers/net/dsa/sja1105/sja1105.h
> > +++ b/drivers/net/dsa/sja1105/sja1105.h
> > @@ -111,6 +111,11 @@ struct sja1105_info {
> >  				enum packing_op op);
> >  	int (*clocking_setup)(struct sja1105_private *priv);
> >  	const char *name;
> > +	bool supports_mii[SJA1105_MAX_NUM_PORTS];
> > +	bool supports_rmii[SJA1105_MAX_NUM_PORTS];
> > +	bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
> > +	bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
> > +	bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
> 
> If you used a bitmap you may be able to play some nice tricks with
> ordering them in PHY_INTERFACE_MODE_* order and just increment a pointer
> to the bitmap.
> 
> Since it looks like all of the chips support MII, RMII, and RGMII on all
> ports, maybe you can specify only those that don't?
> 
> Still:
> 
> Reviewed-by: Florian Fainelli <f.fainelli@...il.com>

Because the SJA1110 doesn't have public documentation, I am making a bit
of a compromise for SJA1105 in order to be very clear about which SJA1110
port supports which PHY interface type. With pointers to the beginning
and end of a phy_interface_t array for each switch type and port number,
it wouldn't be quite as clear, in fact it might end up quite a bit
messy.