netdev - [PATCH v3 net-next 0/8] Part 2 of SJA1105 DSA driver preparation for new switch introduction (SJA1110)

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Message-Id: <20210530225939.772553-1-olteanv@gmail.com>
Date:   Mon, 31 May 2021 01:59:31 +0300
From:   Vladimir Oltean <olteanv@...il.com>
To:     Jakub Kicinski <kuba@...nel.org>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Vladimir Oltean <vladimir.oltean@....com>,
        Russell King <linux@...linux.org.uk>,
        Heiner Kallweit <hkallweit1@...il.com>
Subject: [PATCH v3 net-next 0/8] Part 2 of SJA1105 DSA driver preparation for new switch introduction (SJA1110)

From: Vladimir Oltean <vladimir.oltean@....com>

This series is a continuation of:
https://patchwork.kernel.org/project/netdevbpf/cover/20210524131421.1030789-1-olteanv@gmail.com/

even though it isn't the first time these patches are submitted (they
were part of the group previously called "Add NXP SJA1110 support to the
sja1105 DSA driver"):
https://patchwork.kernel.org/project/netdevbpf/cover/20210526135535.2515123-1-vladimir.oltean@nxp.com/

but I broke that up again since these patches are already reviewed, for
the most part. There are no changes compared to v2 and v1.

This series of patches contains:

- an adaptation of the driver to the new "ethernet-ports" OF node name
- an adaptation of the driver to support more than 1 SGMII port
- a generalization of the supported phy_interface_t values per port
- an adaptation to encode SPEED_10, SPEED_100, SPEED_1000 into the
  hardware registers differently depending on switch revision
- a consolidation of the PHY interface type used for RGMII and another
  one for the API exposed for sja1105_dynamic_config_read()

Cc: Russell King <linux@...linux.org.uk>
Cc: Heiner Kallweit <hkallweit1@...il.com>

Vladimir Oltean (8):
  net: dsa: sja1105: be compatible with "ethernet-ports" OF node name
  net: dsa: sja1105: allow SGMII PCS configuration to be per port
  net: dsa: sja1105: the 0x1F0000 SGMII "base address" is actually
    MDIO_MMD_VEND2
  net: dsa: sja1105: cache the phy-mode port property
  net: dsa: sja1105: add a PHY interface type compatibility matrix
  net: dsa: sja1105: add a translation table for port speeds
  net: dsa: sja1105: always keep RGMII ports in the MAC role
  net: dsa: sja1105: some table entries are always present when read
    dynamically

 drivers/net/dsa/sja1105/sja1105.h             |  24 +-
 drivers/net/dsa/sja1105/sja1105_clocking.c    |  29 +--
 .../net/dsa/sja1105/sja1105_dynamic_config.c  |  15 +-
 drivers/net/dsa/sja1105/sja1105_main.c        | 207 ++++++++++--------
 drivers/net/dsa/sja1105/sja1105_spi.c         |  63 +++++-
 5 files changed, 206 insertions(+), 132 deletions(-)

-- 
2.25.1