netdev - [PATCH v3 net-next 4/4] net: phy: nxp-c45-tja11xx: enable MDIO write access to the master/slave registers

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Message-Id: <20210614134441.497008-5-olteanv@gmail.com>
Date:   Mon, 14 Jun 2021 16:44:41 +0300
From:   Vladimir Oltean <olteanv@...il.com>
To:     Jakub Kicinski <kuba@...nel.org>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>,
        Radu Pirea <radu-nicolae.pirea@....nxp.com>,
        Vladimir Oltean <vladimir.oltean@....com>,
        Russell King <rmk+kernel@...linux.org.uk>
Subject: [PATCH v3 net-next 4/4] net: phy: nxp-c45-tja11xx: enable MDIO write access to the master/slave registers

From: Vladimir Oltean <vladimir.oltean@....com>

The SJA1110 switch integrates TJA1103 PHYs, but in SJA1110 switch rev B
silicon, there is a bug in that the registers for selecting the 100base-T1
autoneg master/slave roles are not writable.

To enable write access to the master/slave registers, these additional
PHY writes are necessary during initialization.

The issue has been corrected in later SJA1110 silicon versions and is
not present in the standalone PHY variants, but applying the workaround
unconditionally in the driver should not do any harm.

Suggested-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@....nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
v2->v3: none
v1->v2: added a comment

 drivers/net/phy/nxp-c45-tja11xx.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
index 7eac58b78c53..91a327f67a42 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -1035,6 +1035,12 @@ static int nxp_c45_config_init(struct phy_device *phydev)
 		return ret;
 	}
 
+	/* Bug workaround for SJA1110 rev B: enable write access
+	 * to MDIO_MMD_PMAPMD
+	 */
+	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1);
+	phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2);
+
 	phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
 			 PHY_CONFIG_AUTO);
 
-- 
2.25.1