netdev - Re: [PATCH] net: phy: Add RGMII_ID/TXID/RXID handling to the DP83822 driver

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Message-ID: <YPHpILw+p2l6cKR9@lunn.ch>
Date:   Fri, 16 Jul 2021 22:16:32 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Marek Vasut <marex@...x.de>
Cc:     netdev@...r.kernel.org, Florian Fainelli <f.fainelli@...il.com>,
        Dan Murphy <dmurphy@...com>,
        "David S . Miller" <davem@...emloft.net>
Subject: Re: [PATCH] net: phy: Add RGMII_ID/TXID/RXID handling to the DP83822
 driver

On Fri, Jul 16, 2021 at 08:23:28PM +0200, Marek Vasut wrote:
> Add support for setting the internal clock shift of the PHY based on
> the interface requirements. RX/TX/both is supported for RGMII.
> 
> Signed-off-by: Marek Vasut <marex@...x.de>
> Cc: Florian Fainelli <f.fainelli@...il.com>
> Cc: Dan Murphy <dmurphy@...com>
> Cc: David S. Miller <davem@...emloft.net>
> ---
>  drivers/net/phy/dp83822.c | 37 +++++++++++++++++++++++++++++++++----
>  1 file changed, 33 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
> index f7a2ec150e54..971c8d6b85d2 100644
> --- a/drivers/net/phy/dp83822.c
> +++ b/drivers/net/phy/dp83822.c
> @@ -72,6 +72,10 @@
>  #define DP83822_ANEG_ERR_INT_EN		BIT(6)
>  #define DP83822_EEE_ERROR_CHANGE_INT_EN	BIT(7)
>  
> +/* RCSR bits */
> +#define DP83822_RGMII_RX_CLOCK_SHIFT	BIT(12)
> +#define DP83822_RGMII_TX_CLOCK_SHIFT	BIT(11)
> +
>  /* INT_STAT1 bits */
>  #define DP83822_WOL_INT_EN	BIT(4)
>  #define DP83822_WOL_INT_STAT	BIT(12)
> @@ -326,11 +330,36 @@ static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
>  
>  static int dp8382x_disable_wol(struct phy_device *phydev)
>  {
> -	int value = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
> -		    DP83822_WOL_SECURE_ON;
> +	u16 val = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | DP83822_WOL_SECURE_ON;
> +
> +	ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
> +				 MII_DP83822_WOL_CFG, val);
> +	if (ret < 0)
> +		return ret;
> +
  
> -	return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
> -				  MII_DP83822_WOL_CFG, value);
> +	return ret;
>  }

This change seems to have nothing to do with RGMII delays.  Please
split it out, so it does not distract from reviewing the real change
here.

It also seems odd you are changing RGMII delays when disabling WOL?
Rebase gone wrong?

	Andrew